MANUFACTURE OF SEMICONDUCTOR DEVICE

    公开(公告)号:JPH08236477A

    公开(公告)日:1996-09-13

    申请号:JP3509295

    申请日:1995-02-23

    Inventor: SAIJO TAKASHI

    Abstract: PURPOSE: To prevent the disconnection of wiring by improving the wiring metal coverage in a contact hole. CONSTITUTION: After a contact hole 4 is formed through an insulating film 3 and a first metallic film 5 is formed on the surface of the film 3 and internal surface of the hole 4, a side wall 6 composed of the film 5 is formed on the internal surface of the lower section of the hole 4 and only the upper section of the hole 4 is tapered by performing isotropic etching on the film 3 around the opening of the hole 4. Since only the upper section of the hole 4 is tapered without changing the bottom size of the hole 4 and, therefore, the aspect ratio of the hole 4 can be reduced, the coverage of a wiring metal composed of a second metallic film 8 can be improved and the disconnection of the wiring can be prevented.

    Chip-size package
    42.
    发明专利
    Chip-size package 审中-公开
    大小包装

    公开(公告)号:JP2008244175A

    公开(公告)日:2008-10-09

    申请号:JP2007083024

    申请日:2007-03-27

    Abstract: PROBLEM TO BE SOLVED: To provide a chip-size package capable of preventing sensor characteristics from being deteriorated at a sensor by external stress from an IC side or residual stress.
    SOLUTION: The chip-size package has: a sensor substrate 1, where the IC E2 is formed around the sensor E1 and a region E3 for junction is formed around the IC; a through-hole wiring formed substrate (a first package substrate) 2; and a cover substrate (a first package substrate) 3. For the sensor substrate 1, a first metal layer 18 for sealing and a first metal layer 19 for electric connection are formed adjacently on the surface of the region E3 for junction. For the through-hole wiring formed substrate 2, a second metal layer 28 for sealing is formed adjacent to a second metal layer 29 for electric connection. For the sensor substrate 1 and the through-hole wiring formed substrate 2, activated junction surfaces of the metal layers 18, 28 for sealing are joined at ordinary temperatures, and the activated junction surfaces of the metal layers 19, 29 for electric connection are joined at ordinary temperatures.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种芯片尺寸封装,其能够防止传感器特性受到来自IC侧的外部应力或残余应力的恶化。 解决方案:芯片尺寸封装具有传感器基板1,其中IC E2围绕传感器E1形成,并且在IC周围形成用于结的区域E3; 通孔布线形成基板(第一封装基板)2; 以及覆盖基板(第一封装基板)3。对于传感器基板1,在用于接合的区域E3的表面上形成有用于密封的第一金属层18和用于电连接的第一金属层19。 对于通孔布线形成基板2,与用于电连接的第二金属层29相邻地形成用于密封的第二金属层28。 对于传感器基板1和通孔布线形成基板2,用于密封的金属层18,28的激活的接合面在常温下接合,并且用于电连接的金属层19,29的激活的接合表面被接合 在常温下。 版权所有(C)2009,JPO&INPIT

    Sensor element
    43.
    发明专利
    Sensor element 审中-公开
    传感器元件

    公开(公告)号:JP2008244169A

    公开(公告)日:2008-10-09

    申请号:JP2007082992

    申请日:2007-03-27

    Abstract: PROBLEM TO BE SOLVED: To provide a sensor element capable of reducing residual stress generated when joining a sensor substrate to a package substrate.
    SOLUTION: In a sensor substrate 1, a first sealing metal layer 18 is formed in a frame shape at one surface side and a first electric connection metal layer 19 connected to a sensing section electrically is formed. In a through hole wiring formation substrate 2 being a first package substrate, a second sealing metal layer 28 in a frame shape is formed on a surface at the side of the sensor substrate 1, and a second electric connection metal layer 29 connected to through hole wiring 24 electrically is formed. In the sensor substrate 1 and the through hole wiring formation substrate 2, activated junction surfaces are joined at ordinary temperatures for metal layers 18, 28 for sealing and metal layers 19, 29 for electric connection. For the sensor substrate 1 and a cover substrate 3 being a second package substrate, the activated junction surfaces are joined at ordinary temperatures by the combination of Si-Si.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种能够减少将传感器基板接合到封装基板时产生的残余应力的传感器元件。 解决方案:在传感器基板1中,第一密封金属层18在一个表面侧以框架形状形成,并且形成电连接到感测部分的第一电连接金属层19。 在作为第一封装基板的贯通孔布线形成基板2中,在传感器基板1侧的表面上形成有框状的第二密封金属层28,与贯通孔连接的第二电连接金属层29 布线24形成。 在传感器基板1和贯通孔配线形成基板2中,为了密封用金属层18,28和电连接用金属层19,29,在常温下接合活化接合面。 对于传感器基板1和作为第二封装基板的盖基板3,通过Si-Si的组合,激活的接合表面在常温下接合。 版权所有(C)2009,JPO&INPIT

    Sensor apparatus
    44.
    发明专利
    Sensor apparatus 审中-公开
    传感器装置

    公开(公告)号:JP2008209163A

    公开(公告)日:2008-09-11

    申请号:JP2007044612

    申请日:2007-02-23

    Abstract: PROBLEM TO BE SOLVED: To provide a sensor apparatus capable of suppressing the effect of disturbances such as electric noise and temperature and achieving high accuracy.
    SOLUTION: A circuit part Dc for processing output signals of a sensor chip 1 is formed on the side opposite to the sensor chip 1 in a first packaging substrate 2. Through-hole wirings 24 to be electrically connected to the sensor chip 1 and the circuit part Dc are formed in the first packaging substrate 2. In the sensor chip 1 and the first packaging substrate 2, a bump 9 formed in the surface of one pad 29 among pads 19 and 29 formed in the opposite surfaces of the sensor chip 1 and the first packaging substrate 2 is joined to the other pad 19 by normal-temperature bump bonding. The circuit part Dc includes a temperature detection part and a temperature compensation circuit.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:提供能够抑制电噪声和温度等干扰的影响并实现高精度的传感器装置。 解决方案:用于处理传感器芯片1的输出信号的电路部分Dc形成在与传感器芯片1相对的一侧的第一封装基板2中。电连接到传感器芯片1的通孔布线24 并且电路部分Dc形成在第一封装基板2中。在传感器芯片1和第一封装基板2中,形成在形成在传感器的相对表面中的焊盘19和29之间的一个焊盘29的表面中的凸块9 芯片1和第一封装基板2通过常温凸点焊接而与另一个焊盘19接合。 电路部分Dc包括温度检测部分和温度补偿电路。 版权所有(C)2008,JPO&INPIT

    Method of manufacturing sensor
    45.
    发明专利
    Method of manufacturing sensor 审中-公开
    制造传感器的方法

    公开(公告)号:JP2008159882A

    公开(公告)日:2008-07-10

    申请号:JP2006347546

    申请日:2006-12-25

    Abstract: PROBLEM TO BE SOLVED: To manufacture a sensor by forming a recess with a desired depth on an upper substrate. SOLUTION: The present invention includes the steps of: manufacturing an upper substrate 4a by laminating an upper surface constitutive substrate 1 and a side surface constitutive substrate 2 via an etching stopper layer 3a; forming a recess on the upper substrate 4a by etching the upper substrate 4a, at the side of the side surface constitutive substrate 2, to the etching stopper layer 3a; mounting a sensor element 6 on a lower substrate 5; and bonding the upper substrate 4a and the lower substrate 5 so as to air-tightly seal the sensor element 6 in the recess. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:通过在上基板上形成具有所需深度的凹部来制造传感器。 解决方案:本发明包括以下步骤:通过经由蚀刻停止层3a层叠上表面构成基板1和侧面构成基板2来制造上基板4a; 通过在侧面构成基板2侧蚀刻上基板4a到蚀刻停止层3a,在上基板4a上形成凹部; 将传感器元件6安装在下基板5上; 并且将上基板4a和下基板5接合,以将传感器元件6气密地密封在凹部中。 版权所有(C)2008,JPO&INPIT

    Sensor device
    46.
    发明专利
    Sensor device 审中-公开
    传感器设备

    公开(公告)号:JP2008157825A

    公开(公告)日:2008-07-10

    申请号:JP2006348632

    申请日:2006-12-25

    Abstract: PROBLEM TO BE SOLVED: To provide a sensor device capable of being reduced in size and height by also providing a circuit part with a dimension about the thickness of a sensing part. SOLUTION: A sensor substrate 1 is provided with a movable part 12 movable relative to a support part 11. The movable part 12 is connected to the support part 11 via a flexure part 13 on one surface side in a displacement direction, and the sensor substrate 1 is provided with a sensing part Ds transducing the displacement of the movable part 12 into an electric quantity. Further, on the other surface side of the movable part 12 in the displacement direction, a circuit part Dc cooperating with the sensing part Ds is formed as an integrated circuit. Through-hole wiring 15 through both surfaces in the displacement direction is formed at the movable part 12, and a part of the through-hole wiring 15 is electrically connected to the circuit part Dc. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种能够通过还提供具有感测部件的厚度的尺寸的电路部件来减小尺寸和高度的传感器装置。 传感器基板1设置有可相对于支撑部分11移动的可移动部分12.可移动部分12经由位移方向的一个表面侧上的挠曲部分13连接到支撑部分11,并且 传感器基板1设置有将可动部12的位移转换为电量的感测部Ds。 此外,在移动部12的位移方向的另一面侧形成有与感测部Ds配合的电路部Dc作为集成电路。 通孔布线15通过位移方向上的两个表面形成在可动部分12上,并且通孔布线15的一部分电连接到电路部分Dc。 版权所有(C)2008,JPO&INPIT

    Sensor module
    47.
    发明专利
    Sensor module 审中-公开
    传感器模块

    公开(公告)号:JP2007266320A

    公开(公告)日:2007-10-11

    申请号:JP2006089587

    申请日:2006-03-28

    Abstract: PROBLEM TO BE SOLVED: To provide a sensor module wherein despite of having its circuit portion cooperating with its sensing portion, its mounting area can be reduced.
    SOLUTION: In the sensor module, a sensor substrate 1 has a sensing portion Ds, and the sensor substrate 1 is interposed in a laminar way between an electrode forming substrate 2 having formed pad-electrodes 25 connected with external circuits and a circuit forming substrate 3 having a formed circuit portion Dc which has an integrated circuit. The sensor substrate 1, the electrode forming substrate 2, and the circuit forming substrate 3 are stuck to each other in a sealing way by joining to each other sealing metal layers 18, 28, 38, 48 which are formed respectively on their peripheral portions. In the sensor substrate 1 and the electrode forming substrate 2, through-hole wirings 24, 44 are so formed as to connect electrically with each other via the through-hole wirings 24, 44 the sensing portion Ds of the sensor substrate 1, the circuit portion Dc of the circuit forming substrate 3, and the pad electrodes 25 of the electrode forming substrate 2. The circuit portion Dc, the sensing portion Ds, and the through-hole wirings 24, 44 are sealed.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:为了提供一种传感器模块,其中尽管其电路部分与其感测部分配合,但是其安装面积可以减小。 解决方案:在传感器模块中,传感器基板1具有感测部分Ds,并且传感器基板1以具有与外部电路连接的形成的焊盘电极25的电极形成基板2和电路之间的层叠方式插入 具有具有集成电路的形成电路部分Dc的形成衬底3。 传感器基板1,电极形成基板2和电路形成基板3以分别形成在其周边部分上的彼此密封金属层18,28,38,48的密封方式彼此粘合。 在传感器基板1和电极形成基板2中,通孔布线24,44形成为经由通孔布线24,44彼此电连接传感器基板1的感测部分Ds,电路 电路形成基板3的部分Dc和电极形成基板2的焊盘电极25.电路部分Dc,感测部分Ds和通孔布线24,44被密封。 版权所有(C)2008,JPO&INPIT

    Chip-size package
    48.
    发明专利
    Chip-size package 有权
    大小包装

    公开(公告)号:JP2007263763A

    公开(公告)日:2007-10-11

    申请号:JP2006089579

    申请日:2006-03-28

    Abstract: PROBLEM TO BE SOLVED: To provide a sensor device capable of preventing deterioration in output characteristics of a sensor part due to external stress from an IC part side. SOLUTION: The sensor device 1 is formed using an SOI wafer that is a semiconductor substrate. The sensor part E1 of the sensor device 1 includes a rectangular frame part 11. A weight part 12 disposed inside the frame part 11 is swingably supported by the frame part 11 via four strip-like flexure parts 13 having flexibility in one surface side. In the sensor part E1, the weight part 12 and respective flexure parts 13 constitute a movable part. The piezoelectric resistors Rx1 to Rx4, Ry1 to Ry4, Rz1 to Rz4 as the sensing part are formed on the movable part. An IC part E2 cooperating with the sensor part E1 and surrounding the sensor part E1 is formed in the sensor device 1. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种能够防止由于来自IC部分侧的外部应力导致的传感器部分的输出特性劣化的传感器装置。 解决方案:传感器装置1使用作为半导体衬底的SOI晶片形成。 传感器装置1的传感器部分E1包括矩形框架部分11.设置在框架部分11内部的配重部分12通过在一个表面侧具有柔性的四个条状弯曲部分13可摆动地支撑在框架部分11上。 在传感器部分E1中,重量部分12和相应的弯曲部分13构成可移动部分。 作为感测部分的压电电阻器Rx1至Rx4,Ry1至Ry4,Rz1至Rz4形成在可动部件上。 传感器装置1中形成有与传感器部E1配合并围绕传感器部E1的IC部E2。(C)2008,JPO&INPIT

    Wafer level package structure and sensor element
    49.
    发明专利
    Wafer level package structure and sensor element 有权
    WAFER LEVEL PACKAGE结构和传感器元件

    公开(公告)号:JP2007194572A

    公开(公告)日:2007-08-02

    申请号:JP2006089557

    申请日:2006-03-28

    CPC classification number: H01L2224/16

    Abstract: PROBLEM TO BE SOLVED: To provide a wafer level package structure capable of improving reliability of hermeticity, and a sensor element.
    SOLUTION: The wafer level package structure 100 has a configuration in which a sensor wafer 10 having a plurality of sensor substrates (sensor bodies) 1 each having a sensing section, a first package wafer 20, and a second package wafer 30 are joined in a wafer level. In the structure 100, frame-like joining metal layers 18 and 28 for the sensor wafer 10 and the first package wafer 20 are directly bonded with each other. In the sensor wafer 10, the metal layer 18 is provided in multilayer; and in the first package wafer 20, the metal layer 28 is provided in multilayer. An acceleration sensor element is formed by dividing the package structure 100 into a predetermined size stipulated on the basis of the size of the sensor substrate 1.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题:提供能够提高气密性的可靠性的晶片级封装结构和传感器元件。 解决方案:晶片级封装结构100具有这样的结构,其中具有多个传感器基板(传感器体)1的传感器晶片10各自具有检测部分,第一封装晶片20和第二封装晶片30 加入了晶圆级。 在结构100中,用于传感器晶片10和第一封装晶片20的框状接合金属层18和28彼此直接接合。 在传感器晶片10中,金属层18设置为多层; 并且在第一封装晶片20中,金属层28设置为多层。 通过将包装结构100分割成基于传感器基板1的尺寸规定的预定尺寸来形成加速度传感器元件。版权所有(C)2007,JPO&INPIT

    Manufacturing method of wafer-level package structure
    50.
    发明专利
    Manufacturing method of wafer-level package structure 有权
    水平包装结构的制造方法

    公开(公告)号:JP2007173634A

    公开(公告)日:2007-07-05

    申请号:JP2005371042

    申请日:2005-12-22

    Abstract: PROBLEM TO BE SOLVED: To provide a forming method of through-hole wiring to a semiconductor wafer with which plating time can be shortened in an electroplating process where a metal as a through-hole wiring is formed to an inner side of a through-hole with a high aspect ratio.
    SOLUTION: A taper-like through-hole 22 whose opening diameter of one surface of the semiconductor wafer 20a is larger than an opening diameter of the other surface is formed by dry etching (Fig. 1(d)). An insulating layer 23 is formed on one surface side and the other surface side of the semiconductor wafer 20a, and on an inner peripheral face of the through-hole 22 (Fig. 1(e)). A conductor part 45 blocking the through-hole 22 is formed on the other surface side of the semiconductor wafer 20a (Fig. 1(g)). An anode is oppositely arranged on one surface side of the semiconductor wafer 20a. A metal 24a of through-hole wiring 24 is deposited from an exposed surface of a through-hole 22-side in a cathode in electroplating along a thickness direction of the semiconductor wafer 20a with the conductor 45 as the cathode.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 解决的问题:为了在电镀工艺中将半导体晶片的通孔布线的形成方法提供给电镀时间可以缩短的电镀工艺,其中作为通孔布线的金属形成在 具有高纵横比的通孔。 解决方案:通过干蚀刻(图1(d))形成半导体晶片20a的一个表面的开口直径大于另一表面的开口直径的锥形通孔22。 绝缘层23形成在半导体晶片20a的一个表面侧和另一个表面侧上,并且在通孔22的内周面(图1(e))上形成。 在半导体晶片20a的另一个表面侧形成有阻挡通孔22的导体部分45(图1(g))。 阳极相对设置在半导体晶片20a的一个表面侧。 以导电体45为阴极,从半导体晶片20a的厚度方向以电镀方式从阴极的通孔22侧的露出面上沉积出通孔配线24的金属24a。 版权所有(C)2007,JPO&INPIT

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