公开(公告)号：HU205511B

公开(公告)日：1992-04-28

申请号：HU802990

申请日：1990-12-03

Applicant: MOTOROLA INC

Inventor： FREEBURG THOMAS A ,  KACZMARCZYK JOHN M ,  NOLAN MICHAEL P ,  BUCHHOLZ DALE R ,  WHITE RICHARD E ,  CHANG HUNGKUN J

IPC: H04L12/54 ,  H04J3/24 ,  H04Q11/04 ,  H04Q7/00

Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.

公开(公告)号：CS9005910A2

公开(公告)日：1991-10-15

申请号：CS591090

申请日：1990-11-28

Applicant: MOTOROLA INC

Inventor： BERKEN JAMES J ,  FREEBURG THOMAS A ,  OGASAWARA ROY T ,  WHITE RICHARD E ,  MITZLAFF JAMES E ,  BEDLEK GREGORY J

IPC: H04B7/24 ,  H04J3/00 ,  H04J3/16 ,  H04L12/28 ,  H04L12/56 ,  H04L5/00

CPC classification number: H04B7/24 ,  H04J3/1682 ,  H04W4/04 ,  H04W72/0453 ,  H04W74/00

公开(公告)号：AU6600490A

公开(公告)日：1991-04-28

申请号：AU6600490

申请日：1990-08-23

Applicant: MOTOROLA INC

Inventor： OGASAWARA ROY T ,  WHITE RICHARD E ,  FREEBURG THOMAS A

IPC: H04L12/64 ,  H04J3/26

公开(公告)号：HU906258D0

公开(公告)日：1991-03-28

申请号：HU625890

申请日：1990-09-28

Applicant: MOTOROLA INC

Inventor： WHITE RICHARD E ,  BUCHHOLZ DALE R ,  JOHANSON LISA B ,  FREEBURG THOMAS A

IPC: H04L12/64

Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.

公开(公告)号：BR9405540A

公开(公告)日：1999-09-08

申请号：BR9405540

申请日：1994-06-27

Applicant: MOTOROLA INC

Inventor： BUCHHOLZ DALE R ,  DOSS WILLIAM K ,  HAMILTON R LEE JR ,  WHITE RICHARD E ,  ROBBINS KAREN

IPC: H04L1/12 ,  H04L1/16 ,  H04L1/18 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08

Abstract: A packet switching system (100) having a packet switch (140) employs an acknowledgement scheme in order assure the delivery of all fragments (310) comprising a fragmented data packet (300) to improve overall system throughput during the handling of packets (310) that require reassembly. When packet fragments (310) are lost, corrupted or otherwise unintelligible to a receiving device (92, 94), the acknowledgement scheme permits retransmission of the missing data. In addition, a second acknowledgment signal is scheduled by system processing resources (110) in order to verify the successful delivery of all retransmitted data.

公开(公告)号：BR9306050A

公开(公告)日：1997-11-18

申请号：BR9306050

申请日：1993-03-22

Applicant: MOTOROLA INC

Inventor： WHITE RICHARD E ,  MCGRATH JAMES ,  BUCHHOLZ DALE R

IPC: H04Q7/38 ,  H04L12/56 ,  H04L12/66 ,  H04L29/06 ,  H04L29/08 ,  H04Q7/22 ,  H04Q7/24 ,  H04Q7/26 ,  H04Q7/30 ,  H04Q11/04 ,  H04J3/24

Abstract: A packet switching system (100) employs packet reassembly hardware (214) in a packet switch (140) to improve overall system throughput during the handling of transmission packets (310) that require reassembly. In this manner, reassembly is accomplished with minimal processor (110) intervention and without having to duplicate the message data portion (312) of a transmission packet (310) into a different memory location prior to retransmission.

公开(公告)号：BR9205487A

公开(公告)日：1994-06-21

申请号：BR9205487

申请日：1992-01-27

Applicant: MOTOROLA INC

Inventor： KACZMARCZYK JOHN M ,  BUCHHOLZ DALE R ,  FREEBURG THOMAS A ,  O'BRIEN RITA ,  WHITE RICHARD E

IPC: H04L29/06 ,  G06F13/42 ,  H04B1/16 ,  H04B1/38 ,  H04M1/73 ,  H04W88/02 ,  H04L12/56

Abstract: A common communication controller (17) is linked to a plurality of peripheral devices (28) by a network interface bus (26). Packets containing information is communicated between the controller and the peripherals over the bus which consists of a parallel packet bus and a plurality of control lines utilized to implement a communication protocol which increases the efficiencies of packet communications by the utilization of additional direct command lines between the communications controller (17) and peripherals (28).

公开(公告)号：MX172698B

公开(公告)日：1994-01-07

申请号：MX2223790

申请日：1990-09-05

Applicant: MOTOROLA INC

Inventor： FREEBURG THOMAS A ,  WHITE RICHARD E ,  BUCHHOLZ DALE R ,  JOHANSON LISA B

IPC: H04L12/64 ,  H04J3/26

Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.

公开(公告)号：NZ236320A

公开(公告)日：1992-10-28

申请号：NZ23632090

申请日：1990-12-03

Applicant: MOTOROLA INC

Inventor： FREEBURG THOMAS A ,  KACZMARCZYK JOHN M ,  BUCHHOLZ DALE R ,  WHITE RICHARD E ,  CHANG HUNGKUN J ,  NOLAN MICHAEL P

IPC: H04L12/54 ,  H04J3/24 ,  H04Q11/04 ,  H04Q7/00

Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.

公开(公告)号：BR9200101A

公开(公告)日：1992-10-06

申请号：BR9200101

申请日：1992-01-15

Applicant: MOTOROLA INC

Inventor： CHANG HUNGKUN J ,  DOSS WILLIAM K ,  NOLAN MICHAEL P ,  BUCCHOLZ DALE R ,  FREEBURG THOMAS A ,  MCKOWN JOHN ,  WHITE RICHARD E

IPC: H04B1/18 ,  H04B7/00 ,  H04B7/08 ,  H04B7/26 ,  H04W16/24 ,  H04W72/08 ,  H04B7/02

Abstract: An antenna selection technique is used in an RF communication system in which user modules (UM1-UM5) communicate with at least one node (N1-N2). The UM's (UM1-UM5) and nodes (N1, N2) each have multiple antennae. The combination of each UM and node antenna is evaluated at the UM. Based on at least signal quality, the UM (UM1-UM5) selects its antenna and the best node antenna for use. An alternate antenna is selected if a person is determined to be present in a predetermined area adjacent a UM (UM1-UM5) corresponding to a predetermined RF power level.