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公开(公告)号：US20200210280A1
公开(公告)日：2020-07-02
申请号：US16267586
申请日：2019-02-05
Applicant: Micron Technology, Inc.
Inventor： Harish Reddy Singidi , Kishore Kumar Muchherla , Xiangang Luo , Vamsi Pavan Rayaprolu , Ashutosh Malshe
Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.
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公开(公告)号：US10671298B2
公开(公告)日：2020-06-02
申请号：US15913157
申请日：2018-03-06
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Kishore Kumar Muchherla , Harish R. Singidi , Ashutosh Malshe , Gianni S. Alsasua
IPC: G06F3/06
Abstract: Data to store at a storage system is received. The storage system includes data blocks and the plurality of blocks that include a first region corresponding to a first storage density and a second region corresponding to a second storage density that is less dense than the first storage density. The data is stored at the first region of the plurality of data blocks that corresponds to the first storage density. A write attribute related to storing the data at the first region of the plurality of data blocks is determined. Thereupon, the write attribute related to storing the data at the first region is stored in the second region of the plurality of data blocks that corresponds to the second storage density.
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公开(公告)号：US10606698B2
公开(公告)日：2020-03-31
申请号：US16164429
申请日：2018-10-18
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Sivagnanam Parthasarathy , Sampath K. Ratnam , Shane Nowell , Renato C. Padilla
Abstract: A determination can be made that an error control operation associated with user data has failed. An initial operating characteristic associated with the error control operation that failed can be identified. A complementary operating characteristic to replace the operating characteristic associated with the error control operation that failed can be determined. The error control operation for the user data can be performed based on the complementary operating characteristic.
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公开(公告)号：US20200026462A1
公开(公告)日：2020-01-23
申请号：US16041649
申请日：2018-07-20
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
IPC: G06F3/06
Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
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公开(公告)号：US20190278491A1
公开(公告)日：2019-09-12
申请号：US15913157
申请日：2018-03-06
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Kishore Kumar Muchherla , Harish R. Singidi , Ashutosh Malshe , Gianni S. Alsasua
IPC: G06F3/06
Abstract: Data to store at a storage system is received. The storage system includes data blocks and the plurality of blocks that include a first region corresponding to a first storage density and a second region corresponding to a second storage density that is less dense than the first storage density. The data is stored at the first region of the plurality of data blocks that corresponds to the first storage density. A write attribute related to storing the data at the first region of the plurality of data blocks is determined. Thereupon, the write attribute related to storing the data at the first region is stored in the second region of the plurality of data blocks that corresponds to the second storage density.
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Patent Agency Ranking
46.发明申请公开(公告)号：US20190252028A1
公开(公告)日：2019-08-15
申请号：US15991822
申请日：2018-05-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sampath K. Ratnam , Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Peter Feeley , Kishore Kumar Muchherla , Renato C. Padilla , Shane Nowell
CPC classification number: G11C16/3427 , G11C7/04 , G11C7/22 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C2207/22
Abstract: A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
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公开(公告)号：US20190243704A1
公开(公告)日：2019-08-08
申请号：US16045641
申请日：2018-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Peter Feeley , Sampath K. Ratnam , Sivagnanam Parthasarathy , Qisong Lin , Shane Nowell , Mustafa N. Kaynak
CPC classification number: G06F11/0793 , G06F3/0619 , G06F3/0634 , G06F3/0679 , G06F11/073 , G06F11/076 , G06F11/079 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
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公开(公告)号：US20250053317A1
公开(公告)日：2025-02-13
申请号：US18928674
申请日：2024-10-28
Applicant: Micron Technology, Inc.
Inventor： Hyungseok Kim , Vamsi Pavan Rayaprolu , Sampath K. Ratnam
Abstract: An example method of performing read operation comprises: receiving a read request with respect to a set of memory cells of a memory device; determining a value of a media endurance metric of the set of memory cells; determining a programing temperature associated with the set of memory cells; determining a current operating temperature of the memory device; determining a voltage adjustment value based on the value of the media endurance metric, the programming temperature, and the current operating temperature; adjusting, by the voltage adjustment value, a bitline voltage applied to a bitline associated with the set of memory cells; and performing, using the adjusted bitline voltage, a read operation with respect to the set of memory cells.
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公开(公告)号：US12131790B2
公开(公告)日：2024-10-29
申请号：US18125595
申请日：2023-03-23
Applicant: Micron Technology, Inc.
Inventor： Ashutosh Malshe , Vamsi Pavan Rayaprolu , Kishore K. Muchherla
IPC: G06F11/10 , G06F3/06 , G06F11/34 , G06F12/02 , G06F12/0891 , G06F16/11 , G06F16/16 , G06F16/17 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/34
CPC classification number: G11C16/3495 , G06F12/0891 , G11C16/102 , G11C16/16 , G11C16/26 , G06F2212/1016 , G06F2212/7201 , G06F2212/7211
Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.
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公开(公告)号：US20240302968A1
公开(公告)日：2024-09-12
申请号：US18666667
申请日：2024-05-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jay Sarkar , Vamsi Pavan Rayaprolu , Ipsita Ghosh
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0629 , G06F3/0679
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including sending, to a device that provides error-handling flow optimization, an ordered set of error-handling operations to be performed to recover data residing in a segment of the memory device; receiving, from the device that provides the error-handling flow optimization, a reordered set of error-handling operations, wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations, wherein the reordered set is obtained by applying the ordered set of error-handling operations to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations, and wherein the latency data for the previously-performed error-handling operations depends on a workload of the segment of the memory device; and performing one or more error-handling operations of the reordered set of error-handling operations to the data residing in the segment of the memory device.
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