公开(公告)号：US20240379147A1

公开(公告)日：2024-11-14

申请号：US18635739

申请日：2024-04-15

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yuan He

IPC: G11C11/4078 ,  G11C11/4093 ,  G11C11/4096

Abstract: Apparatuses and techniques for implementing aspects of proactive usage-based disturbance mitigation based on resource availability are described. In an example aspect, usage-based disturbance circuitry of a memory device performs usage-based disturbance mitigation based on multiple criteria. A primary criterion is associated with normal usage-based disturbance mitigation and can enable the memory device to balance power consumption with usage-based disturbance mitigation. At least one secondary criterion is less strict compared to the primary criterion. While a resource is available, the usage-based disturbance circuitry can proactively mitigate usage-based disturbance based on activated rows that satisfy the secondary criterion but don't yet satisfy the primary criterion. With these preemptive measures, the usage-based disturbance circuitry can reduce a probability of a waterfall event causing a denial-of-service (DOS) situation while the resource is available. If the resource becomes limited, the usage-based disturbance circuitry temporarily disables proactive usage-based disturbance mitigation until the resource becomes available again.

公开(公告)号：US20240363191A1

公开(公告)日：2024-10-31

申请号：US18634096

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yuan He ,  Kang-Yong Kim ,  Dong Pan

IPC: G11C29/00

CPC classification number: G11C29/76 ,  G11C29/789

Abstract: Apparatuses and techniques for implementing usage-based disturbance (UBD) counter repair are described. In example implementations, a memory device includes multiple memory rows, multiple corresponding UBD counters, a register, and a spare UBD counter. If a UBD counter is faulty, logic can substitute the spare UBD counter. To do so, the logic can store a row address corresponding to the faulty UBD counter in the register. The logic can increment a value in the spare UBD counter responsive to a row activation corresponding to the stored row address. A mitigation procedure on a row that may be affected by the activation can be performed based on the value. A host device can control, at least partially, the UBD counter repair process. In these manners, a repair of a faulty UBD counter can be accomplished faster and/or with fewer resources as compared to replacing a memory row and corresponding UBD counter.

公开(公告)号：US20240312499A1

公开(公告)日：2024-09-19

申请号：US18672339

申请日：2024-05-23

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Yang Lu

IPC: G11C7/10 ,  H03K19/017 ,  H03K19/173

CPC classification number: G11C7/109 ,  G11C7/1087 ,  H03K19/01742 ,  H03K19/1737

Abstract: The subject application is directed to die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

公开(公告)号：US12020771B2

公开(公告)日：2024-06-25

申请号：US17818413

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Yang Lu

IPC: G11C7/10 ,  H03K19/017 ,  H03K19/173

CPC classification number: G11C7/109 ,  G11C7/1087 ,  H03K19/01742 ,  H03K19/1737

Abstract: Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

公开(公告)号：US20240071461A1

公开(公告)日：2024-02-29

申请号：US17823407

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4096

Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.

公开(公告)号：US20240070102A1

公开(公告)日：2024-02-29

申请号：US17823423

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Creston M. Dupree ,  Smruti Subhash Jhaveri ,  Hyun Yoo Lee ,  John Christopher Sancon ,  Kang-Yong Kim ,  Francesco Douglas Verna-Ketel

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1668

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

公开(公告)号：US20240070096A1

公开(公告)日：2024-02-29

申请号：US17823432

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Creston M. Dupree ,  Kang-Yong Kim

IPC: G06F13/16 ,  G06F11/07

CPC classification number: G06F13/1689 ,  G06F11/0772 ,  G06F13/1663

Abstract: Described apparatuses and methods relate to erroneous select die access (SDA) detection for a memory system. A memory system may include a memory controller and a memory device that are capable of implementing an SDA protocol that enables selective memory die access to multiple memory devices that couple to a command bus. A memory device can include logic that determines if signaling that conflicts with the SDA protocol is detected. If it is determined that conflicting signaling is detected, the logic may provide an indication of the conflicted signaling. In doing so, the erroneous SDA detection described herein may reduce the likelihood of a memory device erroneously masking memory dice, thereby limiting the memory device from exhibiting unexpected, and in some cases, dangerous behavior.

公开(公告)号：US20240029778A1

公开(公告)日：2024-01-25

申请号：US17871752

申请日：2022-07-22

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G11C11/406

CPC classification number: G11C11/40618

Abstract: In various examples, refreshing a bank can include receiving a refresh command, wherein the refresh command comprises selector bits and receiving mode register bits from the mode registers. Refreshing a bank can also include refreshing a number of banks from the plurality of banks utilizing the mode register bits and the selector bits.

公开(公告)号：US20230396272A1

公开(公告)日：2023-12-07

申请号：US17969856

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Yang Lu

IPC: H03M13/15 ,  H03M13/09 ,  G06F13/42

CPC classification number: H03M13/152 ,  H03M13/095 ,  G06F13/4221

Abstract: Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.

公开(公告)号：US20230307030A1

公开(公告)日：2023-09-28

申请号：US17656801

申请日：2022-03-28

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4085 ,  G11C11/4076

Abstract: Described apparatuses and methods relate to adaptive wordline refresh for a memory system that may support a nondeterministic protocol. To help manage power delivery networks in a memory system, a memory device can include logic that can stagger activation of multiple wordlines that are to be activated or refreshed approximately simultaneously. The logic circuitry can be coupled between wordlines that are to be activated and delay propagation of the activation signal. Thus, a first group of wordlines (e.g., “before” the logic circuitry) are activated by the signal, but activation of a second group of wordlines (e.g., “after” the logic circuitry), is delayed, reducing the peak current draw. Additional logic circuitries can be coupled between the wordlines to divide the wordlines into multiple groups, thereby staggering the activation of wordlines that are activated by a refresh command, which can reduce the peak current draw and power consumption.