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公开(公告)号：DE3683522D1
公开(公告)日：1992-03-05
申请号：DE3683522
申请日：1986-04-08
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: A modulator/demodulator operation mode control system (40) specifies an operation mode, which is a combination of particular data transmission rate, multi-phase PSK modulation system, error-correction coding rate and others, in which a modulator/demodulator is to operate, while deciding the operation mode and controlling the modulator demodulator. A transmit station designates a particular operation mode in a plurality of bits in terms of polarities of unique words, while a receive station switches a demodulator (42) thereof to the designated operation mode responsive to an output of mode switchover signal decision means (50) and based on signal representative of detection of the unique words.
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公开(公告)号：CA1252923A
公开(公告)日：1989-04-18
申请号：CA517736
申请日：1986-09-09
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: An FDM-TDM transmultiplexing system for a modulation/demodulation device which is applicable to a regenerative repeating system of a satellite or a ground radio communication system is disclosed which uses chirp-z-transform. A chirp filter is implemented with a digital circuit. The circuit scale of the digital chirp filter increases in proportion to a square root of the total number of channels N, enhancing miniaturization of an FDM-TDM transmultiplexer.
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公开(公告)号：DE69233486T2
公开(公告)日：2005-07-28
申请号：DE69233486
申请日：1992-09-18
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H04L27/00 , H04L27/22 , H04L27/233
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公开(公告)号：DE69729681T2
公开(公告)日：2004-12-09
申请号：DE69729681
申请日：1997-04-14
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: A variable-bandwidth frequency-division multiplex communication system which needs no interpolation circuits, but uses switch element of simple structure. The system includes a signal combining circuit which has N A/D converters associated respectively with independent information signals to be transmitted, a complex local oscillator for generating complex signals each having a frequency k DELTA f (1 ≤ k≤ N-1), DELTA f being the channel frequency interval, N complex multipliers for multiplying the outputs of the A/D converters by the respective complex signals, and producing N output signals, a circuit for effecting an inverse Fourier transform of N points, an N x N switch circuit connected between the outputs of the complex multipliers and input terminals of the inverse Fourier transform circuit, N digital subfilters connected respectively to the outputs of the inverse Fourier transform circuit, N delay units connected respectively to outputs of the digital subfilters, and an adder for adding output signals from the delay units and outputting a sum signal.
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Patent Agency Ranking
公开(公告)号：DE69231879T2
公开(公告)日：2001-12-20
申请号：DE69231879
申请日：1992-09-21
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H04L27/00 , H04L27/22 , H04L27/233
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公开(公告)号：DE69231879D1
公开(公告)日：2001-07-26
申请号：DE69231879
申请日：1992-09-21
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H04L27/00 , H04L27/22 , H04L27/233
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公开(公告)号：CA2078636C
公开(公告)日：1998-05-26
申请号：CA2078636
申请日：1992-09-18
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H04L27/00 , H04L27/22 , H04L27/233 , H03D3/00
Abstract: For processing a multiplied signal into a modified signal in a demodulator circuit, an adder (34) sums up a first, a second, and a third processed signal into a sum signal for use as the modified signal. A first processing circuit (31) processes the multiplied signal into the first processed signal. A second processing circuit (32) processes the multiplied signal into the second processed signal in accordance with a conjugate complex clock and a complex local signal. A third signal processing circuit (33) processes the multiplied signal into the third processed signal in accordance with a complex clock and a conjugate complex local signal. The complex clock signal represents a first complex number. The complex local signal represents a second complex number. The conjugate complex clock signal represents a complex conjugate of the first complex number. The conjugate complex local signal represents a complex conjugate of the second complex number.
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公开(公告)号：DE69216972D1
公开(公告)日：1997-03-06
申请号：DE69216972
申请日：1992-09-29
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
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公开(公告)号：DE3855244T2
公开(公告)日：1997-01-02
申请号：DE3855244
申请日：1988-02-16
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: An N-channel FDM signal is converted into complex signals of baseband frequencies (1-6) spaced at intervals equal to frequency DELTA f. The complex baseband signals are converted first into digital samples (7-9)having a frequency N DELTA f and then into N parallel digital signals (11). A plurality of first FIR subfilters (17-1 through 17-N) respectively perform filtering on each of the parallel digital signals at frequency DELTA f to produce a first series of filtered digital signals from each of the first FIR subfilters, and (m - 1) groups of second FIR subfilters respectively perform filtering on each of the parallel digital signals at frequency DELTA f to produce a second series of filtered digital samples from each of the second FIR subfilters at timing displaced with respect to the first series by a/m DELTA f, where is an integer ranging from unity to (m - 1) and m is an integer equal to or greater than 2. Outputs of the first FIR subfilters are combined with outputs of the second FIR subfilters to produce N summation outputs at frequency m DELTA f. An N-point Fast Fourier Transform processor (14) performs fast Fourier transform on the N summation outputs at frequency m DELTA f to derive digital channels. Because of the oversampling at frequency m DELTA f, each of the digital channels has a frequency response which can be made flat over the bandwidth DELTA f.
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