41.
    发明专利
    未知

    公开(公告)号:BR0108969A

    公开(公告)日:2006-05-09

    申请号:BR0108969

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

    42.
    发明专利
    未知

    公开(公告)号:BRPI0407766A

    公开(公告)日:2006-03-01

    申请号:BRPI0407766

    申请日:2004-02-23

    Applicant: QUALCOMM INC

    Abstract: A forward link repeater frequency watermarking (FLRFWM) system and method that enable accurate position location of mobile stations in areas where repeaters are present by watermarking repeated signals with repeater information. A repeater watermarks a forward link signal with a (unique or non-unique) fast frequency modulation waveform watermark every time a signal passes through the repeater. A mobile station detects and/or identifies the fast frequency watermark on the forward link signal to determine repeater information that aids the network position determination entity or mobile station position location system in determining position location using AFLT and/or A-GPS systems. A forward link fast frequency watermarking system described herein achieves minimal impact on FL, AFLT, and GPS performance, good detection, identification and false alarm probabilities, short time-to-detect/identify, and good detection/identification sensitivity.

    Forward link repeater frequency watermarking system

    公开(公告)号:AU2004214826A1

    公开(公告)日:2004-09-10

    申请号:AU2004214826

    申请日:2004-02-23

    Applicant: QUALCOMM INC

    Abstract: A forward link repeater frequency watermarking (FLRFWM) system and method that enable accurate position location of mobile stations in areas where repeaters are present by watermarking repeated signals with repeater information. A repeater watermarks a forward link signal with a (unique or non-unique) fast frequency modulation waveform watermark every time a signal passes through the repeater. A mobile station detects and/or identifies the fast frequency watermark on the forward link signal to determine repeater information that aids the network position determination entity or mobile station position location system in determining position location using AFLT and/or A-GPS systems. A forward link fast frequency watermarking system described herein achieves minimal impact on FL, AFLT, and GPS performance, good detection, identification and false alarm probabilities, short time-to-detect/identify, and good detection/identification sensitivity.

    Method for adjusting gain of circuit element in transmitter

    公开(公告)号:HK1060404A1

    公开(公告)日:2004-08-06

    申请号:HK04103282

    申请日:2004-05-11

    Applicant: QUALCOMM INC

    Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

    Transmitter architectures for communications systems

    公开(公告)号:AU4338401A

    公开(公告)日:2001-09-17

    申请号:AU4338401

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

    TRANSMITTER ARCHITECTURES FOR COMMUNICATIONS SYSTEMS

    公开(公告)号:CA2702881A1

    公开(公告)日:2001-09-13

    申请号:CA2702881

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

    DIGITAL-TO-ANALOG INTERFACE CIRCUIT HAVING ADJUSTABLE TIME RESPONSE
    47.
    发明申请
    DIGITAL-TO-ANALOG INTERFACE CIRCUIT HAVING ADJUSTABLE TIME RESPONSE 审中-公开
    具有可调节时间响应的数字到模拟接口电路

    公开(公告)号:WO0167591A9

    公开(公告)日:2003-01-09

    申请号:PCT/US0106803

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: An interface circuit for converting a digital signal to an analog signal. The interface circuit includes a time response adjustment circuit, a modulator, and a filter. The time response adjustment circuit receives the digital signal and generates an adjusted signal. The modulator couples to the time response adjustment circuit, receives the adjusted signal, and generates a modulator signal. The filter couples to the modulator, receives the modulator signal, and generates the analog signal. The analog signal has a time response that is modified by the time response adjustment circuit. In an embodiment, the time response adjustment circuit includes a gain element, a delay element, and a summer. The gain element receives and scales the digital signal by a scaling factor. The delay element receives and delays the digital signal by a time delay. The summer couples to the gain element and the delay element, sums the scaled signal from the gain element and the delayed signal from the delay element to generate the adjusted signal.

    Abstract translation: 一种用于将数字信号转换为模拟信号的接口电路。 接口电路包括时间响应调整电路,调制器和滤波器。 时间响应调整电路接收数字信号并产生调整信号。 调制器耦合到时间响应调整电路,接收经调整的信号,并产生调制器信号。 滤波器耦合到调制器,接收调制器信号,并产生模拟信号。 模拟信号具有由时间响应调整电路修改的时间响应。 在一个实施例中,时间响应调整电路包括增益元件,延迟元件和加法器。 增益元件以缩放因子接收和缩放数字信号。 延迟元件接收并延迟数字信号延时。 加法器与增益元件和延迟元件耦合,将来自增益元件的定标信号和来自延迟元件的延迟信号相加,以产生调整后的信号。

    FORWARD LINK REPEATER FREQUENCY WATERMARKING SYSTEM
    48.
    发明申请
    FORWARD LINK REPEATER FREQUENCY WATERMARKING SYSTEM 审中-公开
    前向链路重复频率水印系统

    公开(公告)号:WO2004077699A8

    公开(公告)日:2005-11-17

    申请号:PCT/US2004005557

    申请日:2004-02-23

    Abstract: A forward link repeater frequency watermarking (FLRFWM) system and method that enable accurate position location of mobile stations in areas where repeaters are present by watermarking repeated signals with repeater information. A repeater watermarks a forward link signal with a (unique or non-unique) fast frequency modulation waveform watermark every time a signal passes through the repeater. A mobile station detects and/or identifies the fast frequency watermark on the forward link signal to determine repeater information that aids the network position determination entity or mobile station position location system in determining position location using AFLT and/or A-GPS systems. A forward link fast frequency watermarking system described herein achieves minimal impact on FL, AFLT, and GPS performance, good detection, identification and false alarm probabilities, short time-to-detect/identify, and good detection/identification sensitivity.

    Abstract translation: 一种前向链路中继器频率水印(FLRFWM)系统和方法,其通过对具有中继器信息的重复信号进行水印来实现移动站在存在中继器的区域中的准确位置定位。 中继器每当信号通过中继器时,对具有(唯一或非唯一)快速频率调制波形水印的前向链路信号进行水印。 移动台在前向链路信号上检测和/或识别快速频率水印,以确定使用AFLT和/或A-GPS系统帮助网络位置确定实体或移动台位置系统确定位置定位的中继器信息。 本文所述的前向链路快速水印系统对FL,AFLT和GPS性能,良好的检测,识别和假警报概率,短时间检测/识别以及良好的检测/识别灵敏度的影响最小。

    TRANSMITTER ARCHITECTURES FOR COMMUNICATIONS SYSTEMS
    49.
    发明申请
    TRANSMITTER ARCHITECTURES FOR COMMUNICATIONS SYSTEMS 审中-公开
    用于通信系统的发射机结构

    公开(公告)号:WO0167621A3

    公开(公告)日:2002-05-02

    申请号:PCT/US0106740

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    CPC classification number: H03G3/3042 H03F2203/7239 H03G1/0088

    Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

    Abstract translation: 用于具有比传统发射机架构更好的性能的通信系统的发射机架构。 这些改进包括以下组合:控制信号的响应时间更快,线性度更好,干扰减少,功耗降低,电路复杂度降低,成本降低。 对于蜂窝应用,这些改进可以导致系统容量增加,电话尺寸更小,通话和待机时间增加,以及对产品的更多接受。 提供电路以加快控制信号的响应时间。 发送信号路径中的各种元件的控制回路被集成。 增益控制机制允许精确调整输出发射功率电平。 提供控制机制以在不需要时将功率放大器或全部发射信号路径断电。 控制发射信号路径中的各种元件的增益以减少输出发射功率的瞬变,并且还确保瞬变向下。

    DIGITAL-TO-ANALOG INTERFACE CIRCUIT HAVING ADJUSTABLE TIME RESPONSE
    50.
    发明申请
    DIGITAL-TO-ANALOG INTERFACE CIRCUIT HAVING ADJUSTABLE TIME RESPONSE 审中-公开
    具有可调节时间响应的数字到模拟接口电路

    公开(公告)号:WO0167591A3

    公开(公告)日:2002-03-07

    申请号:PCT/US0106803

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: An interface circuit for converting a digital signal to an analog signal. The interface circuit includes a time response adjustment circuit, a modulator, and a filter. The time response adjustment circuit receives the digital signal and generates an adjusted signal. The modulator couples to the time response adjustment circuit, receives the adjusted signal, and generates a modulator signal. The filter couples to the modulator, receives the modulator signal, and generates the analog signal. The analog signal has a time response that is modified by the time response adjustment circuit. In an embodiment, the time response adjustment circuit includes a gain element, a delay element, and a summer. The gain element receives and scales the digital signal by a scaling factor. The delay element receives and delays the digital signal by a time delay. The summer couples to the gain element and the delay element, sums the scaled signal from the gain element and the delayed signal from the delay element to generate the adjusted signal.

    Abstract translation: 一种用于将数字信号转换为模拟信号的接口电路。 接口电路包括时间响应调整电路,调制器和滤波器。 时间响应调整电路接收数字信号并产生调整信号。 调制器耦合到时间响应调整电路,接收经调整的信号,并产生调制器信号。 滤波器耦合到调制器,接收调制器信号,并产生模拟信号。 模拟信号具有由时间响应调整电路修改的时间响应。 在一个实施例中,时间响应调整电路包括增益元件,延迟元件和加法器。 增益元件以缩放因子接收和缩放数字信号。 延迟元件接收并延迟数字信号延时。 加法器与增益元件和延迟元件耦合,将来自增益元件的定标信号和来自延迟元件的延迟信号相加,以产生调整后的信号。

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