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    SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
    41.
    发明专利
    SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效

    公开(公告)号：JPH10321843A

    公开(公告)日：1998-12-04

    申请号：JP12738597

    申请日：1997-05-16

    Applicant: SONY CORP

    Inventor： NAKAMURA MITSUHIRO ,  NAKAMURA YASUNOBU

    IPC: H01L21/28 ,  H01L21/266 ,  H01L21/336 ,  H01L21/337 ,  H01L21/338 ,  H01L29/78 ,  H01L29/808 ,  H01L29/812

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method, whose precision of a distance between a gate and a drain is high and withstand voltage variation is small accordingly. SOLUTION: With respect to a photoresist film 3 to be applied first to a substrate 1, patterning for forming an alignment mark for forming window 4, a source for forming window 5, and a drain for forming window 6 is performed, and an alignment mark 11, a source (n -region) 7, and a drain (n - region) 8 are formed. With respect to a photoresist film 18 to be formed afterwards by lapping, patterning for forming a gate for forming window 19 is performed with the alignment mark 11 as a reference, and a gate (p -region) 20 is formed in the substrate 1.

    SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
    42.
    发明专利
    SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效

    公开(公告)号：JPH09102585A

    公开(公告)日：1997-04-15

    申请号：JP28465495

    申请日：1995-10-05

    Applicant: SONY CORP

    Inventor： NAKAMURA MITSUHIRO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/095

    Abstract: PROBLEM TO BE SOLVED: To reduce a capacitor area in a semiconductor device having at least a transistor and a capacitor together with manufacturing such a semiconductor device with a simple manufacturing device. SOLUTION: In a semiconductor device such as an MMIC, an electrode 17 for capacitor is formed of an ohmic metal of the same layer as of a source electrode 12 and a drain electrode 13 of an FET. On a capacitor constituted of this electrode 17, an interlayer insulating film 5 and an electrode 21, a capacitor to be constituted of the electrode 21, an interlayer insulating film 23 and a wiring consisting of a soldered layer 25 is laminated and these capacitors are connected in parallel. In another embodiment, an electrode for capacitor is further formed by an ohmic metal of the same layer with a gate electrode 11, a three-layer capacitor including a capacitor to be constitutes of this electrode, an interlayer insulating film 4 the electrode 17 is laminated so as to connect these capacitors in parallel.

    TELEVISION RECEIVER
    43.
    发明专利
    TELEVISION RECEIVER 失效

    公开(公告)号：JPH02149191A

    公开(公告)日：1990-06-07

    申请号：JP30328588

    申请日：1988-11-30

    Applicant: SONY CORP

    Inventor： TSURUMOTO TAKASHI ,  TAKAHASHI YASUSHI ,  NAKAMURA MITSUHIRO

    IPC: H04N5/445 ,  H04N5/46

    Abstract: PURPOSE:To avoid unnaturality by displaying a user control quantity such as volume and color to a blank caused when a picture of the existing standard broadcast is displayed on the screen of a television receiver having the screen whose aspect ratio is 16:9. CONSTITUTION:In a television receiver 10 having a screen whose aspect ratio is 16:9, a user control quantity such as a volume or a color is displayed on a blank 21 caused when a picture of the existing standard broadcast is displayed on the screen. That is, a user control data CD is supplied from a terminal 12 and a display pattern 22 corresponding to the user control data CD is generated from a graphic generating circuit 7 together with the signal of the blank screen. Thus, the blank part 21 is utilized effectively and the unnaturality caused when the pattern of the NTSC system is displayed on the received screen of the high definition television set 10 is avoided.

    Electronic equipment
    47.
    发明专利
    Electronic equipment 审中-公开
    电子设备

    公开(公告)号：JP2010218102A

    公开(公告)日：2010-09-30

    申请号：JP2009062753

    申请日：2009-03-16

    Applicant: Sony Corp ,  ソニー株式会社

    Inventor： FUKUMA YOHEI ,  MORISAWA RUI ,  NAKAMURA MITSUHIRO ,  YONEDA TADASHI

    IPC: G06F1/16 ,  H04M1/12

    CPC classification number: F16G13/18 ,  F16M11/10 ,  F16M11/40 ,  F16M13/00 ,  F16M2200/022 ,  F16M2200/024 ,  G06F1/1679 ,  G06F1/1681 ,  H04M1/0216

    Abstract: PROBLEM TO BE SOLVED: To provide electronic equipment for freely adjusting the attitude of a display part by an articulated coupling member whose axial diameter is small.
    SOLUTION: A body part 3 is connected through an articulated coupling member 4 equipped with coupling plates 21 to 28 coupled in series so as to be freely rotated, and gears 41 to 51 interlocking the rotations of the coupling plates 21 to 28 are formed in the coupling plates 21 to 28. Thus, it is possible to distribute torque necessary for holding the attitude of the display part 2 to the body 3 at each coupling place of the plurality of coupling plates 21 to 28 whose axial diameter R1 or the like is small, and it is possible to freely adjust the attitude of the display part 2.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种电子设备，用于通过轴向直径小的铰接联接构件自由地调节显示部分的姿态。 解决方案：主体部分3通过铰接的联接构件4连接，联接构件4配备有联接板21至28以便自由旋转，并且将联接板21至28的旋转联锁的齿轮41至51是 因此，可以在轴向直径R1或者多个连接板21〜28的多个连接板21〜28的各连接位置处分配用于将显示部2的姿势保持在主体3上所需的扭矩 喜欢很小，可以自由调整显示部分2的姿态。版权所有（C）2010，JPO＆INPIT

    PROTECTIVE CIRCUIT FOR FIELD EFFECT TRANSISTOR
    48.
    发明专利
    PROTECTIVE CIRCUIT FOR FIELD EFFECT TRANSISTOR 失效

    公开(公告)号：JP2001332567A

    公开(公告)日：2001-11-30

    申请号：JP2000150349

    申请日：2000-05-22

    Applicant: SONY CORP

    Inventor： NAKAMURA MITSUHIRO

    IPC: H01L27/04 ,  H01L21/338 ,  H01L21/822 ,  H01L27/095 ,  H01L29/778 ,  H01L29/812

    Abstract: PROBLEM TO BE SOLVED: To provide a protective circuit for a field effect transistor having a configuration to be manufactured without increasing constraints on a pattern layout and processes. SOLUTION: The present protective circuit for the field effect transistor 10 is a protective circuit for a Schottky gate HFET in which a series of diodes 14 including 5 diodes 12 connected in series in the normal direction and one diode 16 in the reverse direction are connected in parallel, and a gate line Vgg connected to the gate electrode of the HFET is grounded via the protective circuit 10. The diodes 12, 16 are the ones integrally formed with the Schottky gate HFET and are constituted as Schottky barrier diodes comprising an n+ GaAs cap layer formed on a GaAs substrate and a Schottky electrode formed on the n+ GaAs cap layer.

    SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
    49.
    发明专利
    SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效

    公开(公告)号：JPH11111927A

    公开(公告)日：1999-04-23

    申请号：JP27257197

    申请日：1997-10-06

    Applicant: SONY CORP

    Inventor： NAKAMURA MITSUHIRO ,  HASE ICHIRO ,  KAWASAKI HIDETOSHI ,  WADA SHINICHI

    IPC: H01L21/22 ,  H01L21/338 ,  H01L27/095 ,  H01L29/778 ,  H01L29/812

    Abstract: PROBLEM TO BE SOLVED: To obtain a resistor layer of a high sheet resistance without damaging the sharpness of a heterojunction interface by diffusing zinc as a P-type impurity into an epitaxial substrate of a compound semiconductor at a high concentration by vapor phase diffusion. SOLUTION: An organic matter of zinc is diffused by vapor phase diffusion into an opening with an SiN film 17 as a selective diffusion mask to form a zinc diffusion resistor layer 16. Then, dimethylzinc or diethylzinc, which is a liquid organic metal is supplied in a gaseous state to the semiconductor substrate with high purity hydrogen as a carrier gas. An AlGaAs layer is deposited on a layer above a GaAs layer and zinc is selectively diffused into the AlGaAs layer, thereby preventing the diffusion of zinc the GaAs layer. By diffusing zinc at 600 deg.C or about, the destruction of a sharp crystal structure in a heterojunction interface can be prevented. Then, the zinc diffusion resistor layer 16 is covered by an insulator and an ormic contact formation section is etched, and metal is deposited on the p-AlGaAs layer, thereby obtaining a resistor including an electrode.

    COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT
    50.
    发明专利
    COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH0758126A

    公开(公告)日：1995-03-03

    申请号：JP21909593

    申请日：1993-08-11

    Applicant: SONY CORP

    Inventor： NAKAMURA MITSUHIRO ,  TAKANO TOMOAKI

    IPC: H01L21/762 ,  H01L21/337 ,  H01L27/095 ,  H01L29/808

    Abstract: PURPOSE:To make it possible to provide a high reliability JFET's by preventing the influence of signal characteristics occurring between mutually adjacent JFET's within semiinsulation region through the formation impurity region maintained to a predetermined electric potential with in semiinsulation regions between respective junction type transistors. CONSTITUTION:An impurity region 8 for isolating mutually adjacent JFET's 10 and 20 is provided within a semiinsulation substrate region 1. And high concentration n-type contact layer 6 is formed within the region of a source 2 and a drain 3, and a guard ring 8 creating a high concentration n-type region is formed. Thereafter, a p-type impurities such as Zn is further diffused on part of the top surface of a channel 5 through a mask thereby forming a p-type region 4, and a p-n junction gate is obtained between the region and the channel 5. The contact layer 6 of the source 2 and drain 3, the p-type region 4 of the gate and the guard ring 8 are respectively provided with metal electrodes 7 as ohmic contacts.

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