公开(公告)号：DE2912756A1

公开(公告)日：1979-11-15

申请号：DE2912756

申请日：1979-03-30

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  OHMURO SHIGERU ,  TOKUHARA MASAHARU

IPC: H04N5/455 ,  H03D1/22 ,  H03D3/20 ,  H03D13/00 ,  H03J7/02 ,  H03J7/04 ,  H04N5/50 ,  H03J3/10 ,  H04B1/30

Abstract: In a system in which an intermediate frequency signal is synchronously detected using an intermediate frequency carrier signal derived from the intermediate frequency signal by means of a tuned circuit and a limiter circuit to remove amplitude variations therefrom, an automatic fine tuning signal is derived in a phase detector to which are fed the intermediate frequency carrier signal after its phase has been shifted 90 degrees in a phase shifter and either the intermediate frequency signal or the intermediate frequency carrier signal. When the intermediate frequency carrier signal is used in the phase detector, a second tuned circuit is used therein and buffering between the two tuned circuits prevents interaction therebetween.

公开(公告)号：AU3420278A

公开(公告)日：1979-09-20

申请号：AU3420278

申请日：1978-03-16

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  KAWAKAMI HIROMI ,  OHMURO SHIGERU ,  TOKUHARA MASAHARU

IPC: H04N5/60 ,  H03G3/34 ,  H04B1/10 ,  H04N5/44 ,  H04N5/455 ,  H04B1/30

Abstract: A muting circuit for a television or AM signal receiver which uses a synchronous detector. The muting circuit includes an input terminal for receiving an amplitude modulated signal, a synchronous detector for detecting such AM signal, a circuit for supplying a reference signal having a predetermined frequency and phase to the synchronous detector, an amplifier, a circuit path for delivering to the amplifier the detected signal produced by the synchronous detector, a level detecting device connected to the output of the synchronous detector for producing an excess signal when the detected signal exceeds a predetermined level, an integrator for producing a muting signal in response to the production over an extended period of time of the excess signal, and a switching device connected to the amplifier for muting the signal produced by the amplifier in response to the production of the muting signal.

公开(公告)号：AU2874777A

公开(公告)日：1979-03-22

申请号：AU2874777

申请日：1977-09-13

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  KAWAKAMI HIROMI ,  TOKUHARA MASAHARU

IPC: H04N5/455 ,  H03D1/22 ,  H03J7/02 ,  H03J7/04 ,  H04B1/26 ,  H04N5/50 ,  H03J3/10 ,  H03J3/16

Abstract: A television receiver has an automatic fine tuning circuit with a first phase-locked loop including a first low pass filter and a synchronous video detector with a second phase-locked loop including a second low pass filter. The cut off frequency of the first low pass filter is selected lower than the cut-off frequency of the second low pass filter, thereby enabling a stable operation of two phase-locked loops simultaneously.

公开(公告)号：AU1692676A

公开(公告)日：1978-02-23

申请号：AU1692676

申请日：1976-08-18

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  TOKUHARA MASAHARU ,  KAWAKAMI HIROMI

IPC: H03F3/191 ,  H03D1/22 ,  H03F3/04 ,  H03F3/42 ,  H03F3/45 ,  H04N5/455

Abstract: An amplifier provides a complete video and sound I.F. signal to a synchronous detector switching circuit, and the switching signal to be applied to the switching circuit is obtained from the same amplifier by connecting a grounded base stage, with its emitter impedance, in series with the amplifier load. The grounded base stage has a load tuned to the I.F. carrier frequency, and the filtered signal from the grounded base is the signal applied as the switching signal to the synchronous detector switching circuit.

公开(公告)号：FR2638044B1

公开(公告)日：1992-10-16

申请号：FR8909899

申请日：1989-07-21

Applicant: SONY CORP

Inventor： MOTOE HISAFUMI ,  KAWASHIMA HIROYUKI ,  TOKUHARA MASAHARU

IPC: H04N5/14 ,  H04N7/12

Abstract: A moving detection circuit which has a difference level generator which includes at least a frame delay circuit, and a vertical correlation detector which is connected to the difference signal generator and including a plurality of filters connected to the difference signal generator. A switching circuit for selecting one of the plurality of filters is provided and a control circuit is connected to the vertical correlation detector so as to control the switching circuit in response to the output level of the vertical correlation detector.

公开(公告)号：MY101926A

公开(公告)日：1992-02-15

申请号：MYPI19872415

申请日：1987-09-30

Applicant: SONY CORP

Inventor： TOKUHARA MASAHARU ,  TAMURA TAKAHIKO

IPC: H04N5/68 ,  H04N5/59 ,  H04N9/16 ,  H04N9/30 ,  H04N9/64

Abstract: A CATHODE RAY TUBE (CRT) DRIVE CONTROL CIRCUIT INCLUDES A FEEDBACK CIRCUIT (4, 5, 12) INTERPOSED BETWEEN A BEAM CURRENT DETECTING CIRCUIT (6 TO 11) AND A SIGNAL PROCESSING CIRCUIT (1) FOR CONTROLLING THE SIGNAL TO BE SUPPLIED TO A CRT (3) IN RESPONSE TO A DETECTED BEAN CURRENT, WHEREBY AT LEAST ONE OF THE CONTRAST LEVEL AND THE BRIGHTNESS LEVEL IS CONTROLLED DEPENDING ON A DETECTED DARK LEVEL. (FIG. 1)

公开(公告)号：DE3679036D1

公开(公告)日：1991-06-06

申请号：DE3679036

申请日：1986-10-23

Applicant: SONY CORP

Inventor： SARUGAKU TOSHIO ,  MOTOE HISAFUMI ,  TOKUHARA MASAHARU ,  HONGU MASAYUKI

IPC: H04N5/265 ,  H04N5/45

Abstract: In a picture-in-picture television receiver, the subpicture signal is A-D converted; the converted digital subpicture signal is latched in response a subpicture clock in synchronism with a subpicture synchronizing signal; the latched signal is latched again and stored in an image memory in response to a main picture synchronizing signal; and the latched signal is read from the image memory in synchronism with the main picture synchronizing signal, in order that the subpicture can stably be inserted in a predetermined area of the main picture by eliminating the unstable data duration during which variation in the subpicture signal is different for each bit signal thereof.

公开(公告)号：AU597595B2

公开(公告)日：1990-06-07

申请号：AU6386386

申请日：1986-10-09

Applicant: SONY CORP

Inventor： SARUGAKU TOSHIO ,  MOTOE HISAFUMI ,  TOKUHARA MASAHARU ,  HONGU MASAYUKI

IPC: H04N5/265 ,  H04N5/45

Abstract: In a picture-in-picture television receiver, the subpicture signal is A-D converted; the converted digital subpicture signal is latched in response a subpicture clock in synchronism with a subpicture synchronizing signal; the latched signal is latched again and stored in an image memory in response to a main picture synchronizing signal; and the latched signal is read from the image memory in synchronism with the main picture synchronizing signal, in order that the subpicture can stably be inserted in a predetermined area of the main picture by eliminating the unstable data duration during which variation in the subpicture signal is different for each bit signal thereof.

公开(公告)号：CA1256983A

公开(公告)日：1989-07-04

申请号：CA520076

申请日：1986-10-08

Applicant: SONY CORP

Inventor： SARUGAKU TOSHIO ,  MOTOE HISAFUMI ,  TOKUHARA MASAHARU ,  HONGU MASAYUKI

IPC: H04N5/265 ,  H04N5/45

Abstract: In a picture-in-picture television receiver, the subpicture signal is A-D converted; the converted digital subpicture signal is latched in response a subpicture clock in synchronism with a subpicture synchronizing signal; the latched signal is latched again and stored in an image memory in response to a main picture synchronizing signal; and the latched signal is read from the image memory in synchronism with the main picture synchronizing signal, in order that the subpicture can stably be inserted in a predetermined area of the main picture by eliminating the unstable data duration during which variation in the subpicture signal is different for each bit signal thereof.

公开(公告)号：AU584951B2

公开(公告)日：1989-06-08

申请号：AU5072685

申请日：1985-12-03

Applicant: SONY CORP

Inventor： KITA HIROYUKI ,  TOKUHARA MASAHARU ,  KAWASHIMA HIROYUKI

IPC: H04N11/20 ,  H04N5/12 ,  H04N7/01

Abstract: A digital scan converter comprises an oscillator (23) providing a clock signal used to scan-convert an input video signal so as thereby to produce a scan-converted output video signal (2.R, 2.G, 2.B), an automatic frequency control circuit (22) for controlling the oscillator (23) in synchronism with a synchronising signal (S H ) separated from the input video signal, and a counter (24) for frequency-dividing the clock signal from the oscillator (23) so as thereby to form a control signal used for controlling blanking of the input video signal. The counter (24) provides also an address signal for a memory (14) in which the video signal is stored temporarily during the scan converting operation. Since a composite blanking pulse for the input video signal is formed in synchronism with the address signal for the memory (14). it is possible to prevent appearance of a jitter of the composite blanking pulse on a display screen.