公开(公告)号：KR850001845B1

公开(公告)日：1985-12-26

申请号：KR810002402

申请日：1981-07-02

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  KIDA HIROYUKI ,  OOMURO SHIGERU ,  TOKUHARA MASAHARU

IPC: H03D1/22 ,  H04N5/455 ,  H04N5/14

公开(公告)号：KR850000272Y1

公开(公告)日：1985-02-25

申请号：KR840013491

申请日：1984-12-18

Applicant: SONY CORP

Inventor： HONKU MASAYUKI ,  OOMURO SIGERU ,  TOKUHARA MASAHARU

IPC: H04N5/60

公开(公告)号：DE3924249C2

公开(公告)日：1999-07-15

申请号：DE3924249

申请日：1989-07-21

Applicant: SONY CORP

Inventor： MOTOE HISAFUMI ,  KAWASHIMA HIROYUKI ,  TOKUHARA MASAHARU

IPC: H04N5/14 ,  H04N5/21 ,  H04N7/24

Abstract: A moving detection circuit which has a difference level generator which includes at least a frame delay circuit, and a vertical correlation detector which is connected to the difference signal generator and including a plurality of filters connected to the difference signal generator. A switching circuit for selecting one of the plurality of filters is provided and a control circuit is connected to the vertical correlation detector so as to control the switching circuit in response to the output level of the vertical correlation detector.

公开(公告)号：DE69120770T2

公开(公告)日：1996-12-12

申请号：DE69120770

申请日：1991-10-22

Applicant: SONY CORP

Inventor： KAWASHIMA HIROYUKI ,  KITA HIROYUKI ,  OBANA SHUICHI ,  TOKUHARA MASAHARU

IPC: H04N5/46 ,  H04N7/01 ,  H04N9/64 ,  H04N5/44

Abstract: A video signal processing circuit used for such a non-interlace television comprises an interfield interpolation circuit for carrying out interfield interpolation by using a video signal before one field of an input video signal to output interpolated line video signals corresponding to respective interline positions in one field, an intrafield interpolation circuit for carrying out intrafield interpolation by using video signals of a plurality of lines of the input video signal to output interpolated line video signals corresponding to respective interline positions in one field, a motion detector for detecting motion of the input video signal, a weighting adder for implementing weighting to an output signal from the interfield interpolation circuit and an output signal from the intrafield interpolation circuit in accordance with a signal from the motion detector to add the weighted output signals, a sequential scan converter for carrying out conversion into a sequential scanning signal on the basis of the input video signal and an output signal from the weighting adder, and a controller for controlling at least the interfield interpolation means in accordance with a television standard system of the input video signal, thereby making it possible to lessen disturbance, e.g., deterioration in the picture quality, etc. occurring in the interlaced scanning.

公开(公告)号：DE68921536T2

公开(公告)日：1995-07-06

申请号：DE68921536

申请日：1989-10-12

Applicant: SONY CORP

Inventor： NAITO HIDEFUMI ,  SARUGAKU TOSHIO ,  TOKUHARA MASAHARU

IPC: H04N5/93 ,  H04N5/95 ,  H04N5/783

公开(公告)号：ES2068868T3

公开(公告)日：1995-05-01

申请号：ES89119000

申请日：1989-10-12

Applicant: SONY CORP

Inventor： NAITO HIDEFUMI ,  SARUGAKU TOSHIO ,  TOKUHARA MASAHARU

IPC: H04N5/93 ,  H04N5/95 ,  H04N5/783

公开(公告)号：CA1322241C

公开(公告)日：1993-09-14

申请号：CA604330

申请日：1989-06-29

Applicant: SONY CORP

Inventor： MOTOE HISAFUMI ,  KAWASHIMA HIROYUKI ,  TOKUHARA MASAHARU

IPC: H04N5/14 ,  H04N7/13 ,  H04N5/21 ,  H04N9/77

Abstract: A moving detection circuit which has a difference level generator which includes at least a frame delay circuit, and a vertical correlation detector which is connected to the difference signal generator and including a plurality of filters connected to the difference signal generator. A switching circuit for selecting one of the plurality of filters is provided and a control circuit is connected to the vertical correlation detector so as to control the switching circuit in response to the output level of the vertical correlation detector.

公开(公告)号：CA1315394C

公开(公告)日：1993-03-30

申请号：CA605024

申请日：1989-07-07

Applicant: SONY CORP

Inventor： MOTOE HISAFUMI ,  TOKUHARA MASAHARU ,  HOSHINO TAKAYA

IPC: G06F5/00 ,  G06T9/00 ,  H03M7/30 ,  H04N7/01 ,  H04N11/04 ,  H04N11/20 ,  H04N19/00 ,  H04N19/426 ,  H04N19/51 ,  H04N19/59 ,  H04N19/85 ,  H03M7/00

Abstract: A time-division bit number circuit that comprises a bit number expansion system and/or a bit number reduction system. The bit number expansion system converts an N bits signal to a 2N bits signal, while the bit number reduction system converts the 2N bits signal to the N bits signal where N is an integer. Thus, according to the time-division bit number circuit, the number of memory can be saved, the area of circuit can be reduced and the pattern area of substrate can be reduced.

公开(公告)号：DE3924249A1

公开(公告)日：1990-01-25

申请号：DE3924249

申请日：1989-07-21

Applicant: SONY CORP

Inventor： MOTOE HISAFUMI ,  KAWASHIMA HIROYUKI ,  TOKUHARA MASAHARU

IPC: H04N5/14

Abstract: A moving detection circuit which has a difference level generator which includes at least a frame delay circuit, and a vertical correlation detector which is connected to the difference signal generator and including a plurality of filters connected to the difference signal generator. A switching circuit for selecting one of the plurality of filters is provided and a control circuit is connected to the vertical correlation detector so as to control the switching circuit in response to the output level of the vertical correlation detector.

公开(公告)号：AU5072685A

公开(公告)日：1986-06-19

申请号：AU5072685

申请日：1985-12-03

Applicant: SONY CORP

Inventor： KITA HIROYUKI ,  TOKUHARA MASAHARU ,  KAWASHIMA HIROYUKI

IPC: H04N11/20 ,  H04N5/12 ,  H04N7/01

Abstract: A digital scan converter comprises an oscillator (23) providing a clock signal used to scan-convert an input video signal so as thereby to produce a scan-converted output video signal (2.R, 2.G, 2.B), an automatic frequency control circuit (22) for controlling the oscillator (23) in synchronism with a synchronising signal (S H ) separated from the input video signal, and a counter (24) for frequency-dividing the clock signal from the oscillator (23) so as thereby to form a control signal used for controlling blanking of the input video signal. The counter (24) provides also an address signal for a memory (14) in which the video signal is stored temporarily during the scan converting operation. Since a composite blanking pulse for the input video signal is formed in synchronism with the address signal for the memory (14). it is possible to prevent appearance of a jitter of the composite blanking pulse on a display screen.