公开(公告)号：US20140306266A1

公开(公告)日：2014-10-16

申请号：US14349632

申请日：2012-10-24

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/739 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

Abstract translation: 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

公开(公告)号：US12141682B2

公开(公告)日：2024-11-12

申请号：US17181595

申请日：2021-02-22

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei Shan ,  Ziyu Li ,  Jun Yang ,  Longxing Shi

IPC: G06N3/063 ,  G06N3/04 ,  G06F119/12

Abstract: The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under “negative margin”, the system can further lower voltage, compress the timing slack, and obtain higher power gain.

公开(公告)号：US12132407B1

公开(公告)日：2024-10-29

申请号：US18735204

申请日：2024-06-06

Applicant: SOUTHEAST UNIVERSITY

Inventor： Qinsong Qian ,  Ziyan Zhou ,  Yufan Wang ,  Qiang Luo ,  Weifeng Sun ,  Longxing Shi

IPC: H02M3/335 ,  H02M1/00 ,  H02M1/088 ,  H02M3/00

CPC classification number: H02M3/33573 ,  H02M1/0009 ,  H02M1/0054 ,  H02M1/088 ,  H02M3/01 ,  H02M3/33576

Abstract: An adaptive load optimization method for a resonant gate drive circuit is provided to optimize the switching loss, turn-on loss and gate drive loss under different MOSFET loads. A data table is pre-stored in a digital signal processor chip (DSP), and voltages and pre-charge times, corresponding to a low total loss, of the resonant gate driver obtained by actual tests in case of different load currents are recorded in the data table; and in actual application, after an analog-to-digital converter terminal (ADC) samples a load current, a load current, closest to the sampled load current, is read from the data table, and the digital signal processor chip (DSP) is enabled to perform table look-up to obtain an optimized voltage and pre-charge time of a gate drive circuit.

公开(公告)号：US12119395B2

公开(公告)日：2024-10-15

申请号：US17762212

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Long Zhang ,  Jie Ma ,  Yan Gu ,  Sen Zhang ,  Jing Zhu ,  Jinli Gong ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7394 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095

Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

公开(公告)号：US12046594B1

公开(公告)日：2024-07-23

申请号：US18638735

申请日：2024-04-18

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long Zhang ,  Weifeng Sun ,  Siyang Liu ,  Chengwu Pan ,  Guiqiang Zheng ,  Longxing Shi

IPC: H01L27/06 ,  H01L23/528 ,  H01L29/20 ,  H01L29/778 ,  H01L29/8605 ,  H01L29/872 ,  H01L49/02 ,  H02M1/08

CPC classification number: H01L27/0605 ,  H01L23/5286 ,  H01L27/0629 ,  H01L27/0635 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/8605 ,  H01L29/872 ,  H02M1/08

Abstract: In the monolithically integrated GaN-based half-bridge circuit, a nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially provided on a conductive substrate, the barrier layer and the channel layer are separated by isolation layers, and a diode, an integrated capacitor, a low-side transistor, a high-side transistor, a first integrated resistor and a second integrated resistor are provided. The half-bridge circuit includes: a low-side transistor and a high-side transistor, wherein a drain of the low-side transistor is connected to a source of the high-side transistor and also connected to an output terminal Vout, and a substrate of the low-side transistor is connected to a substrate of the high-side transistor, wherein a series resistor is connected in parallel to a drain of the high-side transistor and a source of the low-side transistor.

公开(公告)号：US11984813B2

公开(公告)日：2024-05-14

申请号：US17435789

申请日：2020-05-15

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shen Xu ,  Siyu Zhao ,  Congming Qi ,  Sen Zhang ,  Xiaoyu Shi ,  Weifeng Sun ,  Longxing Shi

IPC: H02M3/335 ,  H02M1/00 ,  H02M1/38

CPC classification number: H02M3/33592 ,  H02M1/0058 ,  H02M1/38

Abstract: A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.

公开(公告)号：US11158708B1

公开(公告)日：2021-10-26

申请号：US16486494

申请日：2018-09-25

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Lizhi Tang ,  Sheng Li ,  Chi Zhang ,  Jiaxing Wei ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/06

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

公开(公告)号：US20150270377A1

公开(公告)日：2015-09-24

申请号：US14439715

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/739 ,  H01L23/528 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L29/7394 ,  H01L23/528 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1008 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

Abstract translation: 具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层 在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有 在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间 区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。 本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

公开(公告)号：US20150008971A1

公开(公告)日：2015-01-08

申请号：US14369652

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

IPC: H03K3/013 ,  H03K3/012

CPC classification number: H03K3/013 ,  G11C11/417 ,  G11C11/419 ,  H03K3/012

Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals. The current compensation circuit can be used for an SRAM bit line leakage current compensation circuit, because the existence of a large leakage current on the SRAM bit line leads to the decreasing of a voltage difference between two ends of the bit line, resulting in that a subsequent circuit cannot correctly identify a signal.

Abstract translation: 公开了一种噪声电流补偿电路。 该电路设有两个输入和输出端子A和B，以及两个控制端子CON和CONF。 控制端子控制补偿电路的工作模式（工作状态和预充电状态）。 补偿电路由7个PMOS晶体管和8个NMOS晶体管组成。 在正常工作状态下，通过检测原始电路中两根信号线的电位变化率的变化，噪声电流补偿电路自动使缓慢放电的原电路的一端缓慢放电，使一端 原始电路快速放电以更快地放电信号，从而消除噪声电流对电路的影响，并为后续电路信号的正确识别提供帮助。 电流补偿电路可以用于SRAM位线漏电流补偿电路，因为SRAM位线上存在大的漏电流导致位线两端之间的电压差减小，导致 后续电路无法正确识别信号。