Patent search ap:("Tessera Page Inc.") AND inv:"Craig Mitchell"

41.

发明授权
Microelectronic elements with post-assembly planarization 有权

公开(公告)号：US09966303B2

公开(公告)日：2018-05-08

申请号：US15600228

申请日：2017-05-19

Applicant: Tessera, Inc.

Inventor： Vage Oganesian , Belgacem Haba , Craig Mitchell , Ilyas Mohammed , Piyush Savalia

IPC: H01L21/768 , H01L23/538 , H01L23/00 , H01L25/10 , H01L25/00 , H01L25/16 , H01L25/11 , H01L23/13 , H01L23/31 , H01L23/498

CPC classification number: H01L21/76819 , H01L21/76877 , H01L23/13 , H01L23/3128 , H01L23/49827 , H01L23/4985 , H01L23/5389 , H01L24/18 , H01L24/19 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/97 , H01L25/105 , H01L25/117 , H01L25/16 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/24227 , H01L2224/24247 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L2224/97 , H01L2225/1023 , H01L2225/1029 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01061 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/07811 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15156 , H01L2924/15165 , H01L2924/15192 , H01L2924/15311 , H01L2924/15313 , H01L2924/15331 , H01L2924/157 , H01L2924/15788 , H01L2924/18161 , Y10T29/49002 , H01L2224/81 , H01L2924/00 , H01L2224/83

Abstract: A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

42.

发明申请
STAGED VIA FORMATION FROM BOTH SIDES OF CHIP 审中-公开

公开(公告)号：US20180114743A1

公开(公告)日：2018-04-26

申请号：US15842080

申请日：2017-12-14

Applicant: Tessera, Inc.

Inventor： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia

IPC: H01L23/48 , H01L21/768 , H01L25/065 , H01L25/00 , H01L23/00 , H01L23/50

CPC classification number: H01L23/481 , H01L21/76898 , H01L23/50 , H01L24/03 , H01L24/05 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/06181 , H01L2224/16145 , H01L2224/32145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2924/01322 , H01L2924/07811 , H01L2924/12042 , H01L2924/14 , H01L2924/00012 , H01L2924/00

Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.

43.

发明申请
ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN 有权
Title translation: 具有嵌入式微电子元件的载体或层叠芯片的活性芯片

公开(公告)号：US20160233165A1

公开(公告)日：2016-08-11

申请号：US15131966

申请日：2016-04-18

Applicant: Tessera, Inc.

Inventor： Vage Oganesian , Ilyas Mohammed , Craig Mitchell , Belgacem Haba , Piyush Savalia

IPC: H01L23/538 , H01L25/00 , H01L25/065 , H01L27/146 , H01L23/31 , H01L23/00

CPC classification number: H01L23/5384 , H01L23/3114 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L27/14621 , H01L27/14627 , H01L27/14645 , H01L29/0657 , H01L2224/0237 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/06181 , H01L2224/13024 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/32145 , H01L2224/73204 , H01L2224/81805 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

Abstract translation: 一种结构，包括具有前表面和后表面的第一半导体芯片以及后表面中的空腔。第二个半导体芯片安装在腔内。第一芯片可以具有从空腔延伸到前表面的通孔，以及用于将附加的微电子元件连接到第一芯片的有源元件的这些通孔内的导体。该结构可以具有与第一芯片单独的体积相当的体积，并且提供多芯片组件的功能。安装在主体的前表面上的主体和半导体材料层的复合芯片类似地可以具有从后表面延伸到主体中的空腔，并且可以具有安装在该空腔中的附加的微电子元件。

44.

发明授权
Multi-function and shielded 3D interconnects 有权

公开(公告)号：US09355948B2

公开(公告)日：2016-05-31

申请号：US14340159

申请日：2014-07-24

Applicant: Tessera, Inc.

Inventor： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia

IPC: H01L21/44 , H01L23/498 , H01L21/683 , H01L23/48 , H01L23/00

CPC classification number: H01L23/49827 , H01L21/6835 , H01L23/481 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/06 , H01L2221/68327 , H01L2221/6834 , H01L2223/6622 , H01L2224/05009 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/0557 , H01L2224/05644 , H01L2224/05647 , H01L2224/06181 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/3011 , H01L2924/00014 , H01L2924/00

Abstract: A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

45.

发明申请
ELECTRICAL BARRIER LAYERS 有权
Title translation: 电子障碍层

公开(公告)号：US20150334829A1

公开(公告)日：2015-11-19

申请号：US14809117

申请日：2015-07-24

Applicant: Tessera, Inc.

Inventor： Cyprian UZOH , Vage OGANESIAN , Ilyas MOHAMMED , Belgacem Haba , Piyush Savalia , Craig Mitchell

IPC: H05K1/09 , H01L23/00

CPC classification number: H01L24/05 , H01L2224/04042 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05169 , H01L2224/056 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01074 , H01L2924/013 , H05K1/09 , H05K3/4007 , H05K2201/032 , H05K2201/0326 , H05K2201/0338

Abstract: A barrier layer includes a variable-composition nickel alloy layer with a minor constituent of boron, carbon, phosphorus, and tungsten varying throughout the nickel alloy layer in a direction from the bottom surface to the top surface of the nickel alloy layer.

Abstract translation: 阻挡层包括在镍合金层的从底面到顶面的方向上遍及镍合金层的硼，碳，磷和钨的次要成分的可变成分的镍合金层。

46.

发明申请
NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS 有权
Title translation: 非线性形成三维导电元件

公开(公告)号：US20150221551A1

公开(公告)日：2015-08-06

申请号：US14686222

申请日：2015-04-14

Applicant: Tessera, Inc.

Inventor： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia

IPC: H01L21/768

CPC classification number: H01L21/76879 , H01L21/76802 , H01L21/76898 , H01L23/481 , H01L23/4985 , H01L23/5226 , H01L24/06 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/00

Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.

Abstract translation: 提供了在基板上形成导电元件的方法和所得到的组件。该方法包括在覆盖设置在基板上的电介质区域上的牺牲层中形成凹槽。槽优选地沿着衬底的倾斜表面延伸。牺牲层优选通过非光刻方法去除，例如用激光烧蚀，机械研磨或喷砂。在沟槽中形成导电元件。可以形成凹槽。凹槽和导电元件可以沿着衬底的任何表面形成，包括在其中形成的沟槽和通孔内，并且可以连接到衬底的前表面和/或后表面上的导电焊盘。导电元件优选通过电镀形成，并且可以或可以不与基板的表面一致。

47.

发明申请
STAGED VIA FORMATION FROM BOTH SIDES OF CHIP 有权
Title translation: 通过芯片的两面形成

公开(公告)号：US20150130077A1

公开(公告)日：2015-05-14

申请号：US14499162

申请日：2014-09-27

Applicant: Tessera, Inc.

Inventor： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia

IPC: H01L23/48 , H01L23/50

CPC classification number: H01L23/481 , H01L21/76898 , H01L23/50 , H01L24/03 , H01L24/05 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/06181 , H01L2224/16145 , H01L2224/32145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2924/01322 , H01L2924/07811 , H01L2924/12042 , H01L2924/14 , H01L2924/00012 , H01L2924/00

Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.

Abstract translation: 制造半导体组件的方法可以包括提供具有前表面，后表面和多个导电焊盘的半导体元件，形成至少一个至少通过相应的一个导电焊盘延伸的孔，形成从所述后表面至少部分地延伸半导体元件的厚度的开口，使得所述至少一个孔和所述开口在前表面和后表面之间的位置相遇，以及形成在所述后表面处暴露的至少一个导电元件以电连接到外部装置，所述至少一个导电元件在所述至少一个孔内延伸并且至少进入所述开口中，所述导电元件与相应的导电垫电连接。

48.

发明申请
Multi-Function and Shielded 3D Interconnects 有权
Title translation: 多功能和屏蔽3D互连

公开(公告)号：US20150021788A1

公开(公告)日：2015-01-22

申请号：US14340159

申请日：2014-07-24

Applicant: Tessera, Inc.

Inventor： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia

IPC: H01L23/498 , H01L23/00

CPC classification number: H01L23/49827 , H01L21/6835 , H01L23/481 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/06 , H01L2221/68327 , H01L2221/6834 , H01L2223/6622 , H01L2224/05009 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/0557 , H01L2224/05644 , H01L2224/05647 , H01L2224/06181 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/3011 , H01L2924/00014 , H01L2924/00

Abstract: A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Abstract translation: 微电子单元包括基本上由半导体材料组成的半导体元件，其具有前表面，后表面，与前表面相邻的多个有源半导体器件，在前表面暴露的多个导电焊盘，以及延伸穿过半导体元件。至少一个导电焊盘可以至少部分地覆盖开口并且可以与至少一个有源半导体器件电连接。微电子单元还可以包括暴露在后表面处以与外部部件连接的第一导电元件，第一导电元件延伸穿过开口并与至少一个导电焊盘电连接，第二导电元件延伸穿过开口并与第一导电元件绝缘。至少一个导电焊盘可以覆盖在第二导电元件的周边边缘上。