公开(公告)号：US09209273B1

公开(公告)日：2015-12-08

申请号：US14463677

申请日：2014-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L21/4763 ,  H01L29/66 ,  H01L27/088 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating a metal gate structure includes providing a substrate on which a dielectric layer, a first trench disposed in the dielectric layer, a first metal layer filling up the first trench, a second trench disposed in the dielectric layer, a second metal layer filling up the second trench are disposed, and the width of the first trench is less than the width of the second trench; forming a mask layer to completely cover the second trench; performing a first etching process to remove portions of the first metal layer when the second trench is covered by the mask layer; and performing a second etching process to concurrently remove portions of the first metal layer and portions of the second metal layer after the first etching process.

Abstract translation: 一种用于制造金属栅极结构的方法，包括：提供基板，其上布置介电层，设置在电介质层中的第一沟槽，填充第一沟槽的第一金属层，设置在电介质层中的第二沟槽，第二金属层 设置填充第二沟槽，并且第一沟槽的宽度小于第二沟槽的宽度; 形成掩模层以完全覆盖所述第二沟槽; 当所述第二沟槽被所述掩模层覆盖时，执行第一蚀刻工艺以去除所述第一金属层的部分; 以及执行第二蚀刻工艺，以在第一蚀刻工艺之后同时去除第一金属层的部分和第二金属层的部分。

公开(公告)号：US09147612B2

公开(公告)日：2015-09-29

申请号：US14088445

申请日：2013-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  I-Ming Tseng ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Po-Chao Tsao ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/338 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/3086 ,  H01L29/6681

Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

Abstract translation: 本发明提供一种用于形成半导体结构的制造方法，其中首先设置基板，在基板上设置硬掩模，然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模，然后进行图案转印处理，将翅片硬掩模和翅片硬掩模的图案转移到基板中，以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧，并进行翅片切割处理，以去除每个假翅片。

公开(公告)号：US09141744B2

公开(公告)日：2015-09-22

申请号：US13968391

申请日：2013-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.

Abstract translation: 提供了一种用于生成布局图案的方法。 首先，将布局图案提供给计算机系统，并将其分为两个子图案和空白图案。 每个子图案具有简单整数比例的间距，并且空白图案在两个子图案之间。 然后，生成多个第一条纹图案和至少两个第二条纹图案。 第一条形图案的边缘与子图案的边缘对齐，并且第一条纹图案具有相等的间隔和宽度。 第二条纹图案的间距或宽度与第一条纹图案的间距或宽度不同。

公开(公告)号：US20150129980A1

公开(公告)日：2015-05-14

申请号：US14078701

申请日：2013-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Ming-Te Wei ,  Shih-Fang Tzou

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A semiconductor structure comprises a substrate, a plurality of fins, an oxide layer and a gate structure. The fins protrude from the substrate and are separated from each other by the oxide layer. The surface of the oxide layer is uniform and even plane. The gate structure is disposed on the fins. The fin height is distance between the top of the fins and the oxide layer, and at least two of the fins have different fin heights.

Abstract translation: 半导体结构包括基板，多个翅片，氧化物层和栅极结构。 翅片从衬底突出并且通过氧化物层彼此分离。 氧化物层的表面均匀均匀。 栅极结构设置在翅片上。 翅片高度是翅片的顶部和氧化物层之间的距离，并且至少两个翅片具有不同的翅片高度。

公开(公告)号：US20150076623A1

公开(公告)日：2015-03-19

申请号：US14025833

申请日：2013-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有NMOS区和PMOS区的衬底; 在NMOS区域和PMOS区域分别形成虚拟栅极; 从所述NMOS区域和所述PMOS区域中的每一个去除所述伪栅极; 在NMOS区域和PMOS区域上形成n型功函数层; 去除PMOS区域中的n型功函数层; 在NMOS区域和PMOS区域上形成p型功函数层; 以及在NMOS区域和PMOS区域的p型功函数层上沉积低电阻金属层。

公开(公告)号：US20150064929A1

公开(公告)日：2015-03-05

申请号：US14018447

申请日：2013-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Shih-Hung Tsai ,  Rai-Min Huang ,  Yu-Ting Lin ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/76224

Abstract: A method of gap filling includes providing a substrate having a plurality of gaps formed therein. Then, an in-situ steam generation oxidation is performed to form an oxide liner on the substrate. The oxide liner is formed to cover surfaces of the gaps. Subsequently, a high aspect ratio process is performed to form an oxide protecting layer on the oxide liner. After forming the oxide protecting layer, a flowable chemical vapor deposition is performed to form an oxide filling on the oxide protecting layer. More important, the gaps are filled up with the oxide filling layer.

Abstract translation: 间隙填充的方法包括提供其中形成有多个间隙的基板。 然后，进行原位蒸汽发生氧化，以在衬底上形成氧化物衬垫。 形成氧化物衬垫以覆盖间隙的表面。 随后，进行高纵横比处理以在氧化物衬垫上形成氧化物保护层。 在形成氧化物保护层之后，进行可流动的化学气相沉积以在氧化物保护层上形成填充氧化物。 更重要的是，间隙填充有氧化物填充层。

公开(公告)号：US20140361352A1

公开(公告)日：2014-12-11

申请号：US13912173

申请日：2013-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Shih-Fang Tzou

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28079 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Abstract translation: 本发明提供一种制造半导体器件的方法，包括以下步骤。 首先，在基板上形成第一层间电介质。 然后，在基板上形成栅电极，其中栅电极的周围被第一层间电介质包围。 之后，在栅电极上形成图案化掩模层，其中图案化掩模层的底表面与第一层间电介质的顶表面平齐。 然后形成第二层间电介质以覆盖图案化掩模层的顶表面和每个侧表面。 最后，在第一层间电介质和第二层间电介质中形成自对准接触结构。

公开(公告)号：US11631679B2

公开(公告)日：2023-04-18

申请号：US17741431

申请日：2022-05-10

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Luo-Hsin Lee ,  Ting-Pang Chung ,  Shih-Han Hung ,  Po-Han Wu ,  Shu-Yen Chan ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L49/02

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.

公开(公告)号：US10943909B2

公开(公告)日：2021-03-09

申请号：US16001949

申请日：2018-06-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L21/76 ,  H01L21/768

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

公开(公告)号：US10937701B2

公开(公告)日：2021-03-02

申请号：US16038196

申请日：2018-07-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Ming-Feng Kuo ,  Li-Chiang Chen

IPC: H01L27/108 ,  H01L21/8234

Abstract: A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.