公开(公告)号：JPH0267817A

公开(公告)日：1990-03-07

申请号：JP22003388

申请日：1988-09-02

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI

IPC: H03K17/16 ,  G11C27/02 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0948

Abstract: PURPOSE:To obtain the RON characteristic of high flatness and to prevent the occurrence of spike at the time of conduction switching by controlling the back gate potential of a MOSFET in accordance with the level of an analog signal at the time of conduction of an analog switch part and generating a compensating current at the time of conduction switching of the analog switch part. CONSTITUTION:When MOSFETs P1 and N1 are in the conductive state, the back gate potential corresponding to an analog signal level VA to be transmitted is supplied to the MOSFET N1 by a back gate potential control circuit 15, and as the result, the back gate effect of the MOSFET N1 is reduced. Meanwhile, since the compensating current having the polarity opposite to that of the charging/discharging current flowing to a junction capacity CSD is generated in a compensation capacity CSDA by a compensating current generating circuit 15A at the time of conduction switching of the analog switch part, effects given to an analog signal line L by these currents are cencelled by each other. Thus, the resistance (RON) characteristic for conduction of high flatness is obtained, and spike does not occur at the time of conduction switching.