公开(公告)号：JPH0981116A

公开(公告)日：1997-03-28

申请号：JP23579595

申请日：1995-09-13

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI

IPC: H04N3/22 ,  G06T3/40 ,  G09G5/00 ,  G09G5/36

Abstract: PROBLEM TO BE SOLVED: To clearly recognize the part of an object which a user wants to see and to display also whole image including surrounding part of the image. SOLUTION: A magnification control part 103 synchronizes with image data read out of an image memory 3 by an image read-out part 102, and outputs magnification specifying information to be applied to each image data. A magnification/reduction operation part 104 operates an image data of each image magnified or reduced according to magnification specifying information and writes the result in a temporary storage 4. An image output part 105 displays the image data in the temporary storage 4 on a display device 2. The value of the magnification specifying signal applied to each image data becomes a maximum magnification corresponding to a view point neighborhood part of designated by a visual field specifying device 5, and is decided so as to become lower as it goes away from the view point neighborhood part.

公开(公告)号：JPH04150418A

公开(公告)日：1992-05-22

申请号：JP27359790

申请日：1990-10-12

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  KISHII TATSUYA ,  MORITA KUNIAKI ,  HOSHI JURO

IPC: H03M3/04 ,  H03H17/00 ,  H03H17/02 ,  H03M3/02 ,  H03M7/00

Abstract: PURPOSE:To obtain a low-noise analog output by frequency-dividing a system clock signal having a frequency fs into

公开(公告)号：JPH04115713A

公开(公告)日：1992-04-16

申请号：JP23519390

申请日：1990-09-05

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  KISHII TATSUYA ,  MORITA KUNIAKI ,  HOSHI JURO

IPC: H03M1/10 ,  H03K5/00

Abstract: PURPOSE:To obtain a pulse output with much less noise by interposing 2nd and 3rd transistors(TRs) turned on in response to a synchronizing pulse with a narrower pulse width than that of a data pulse in series between an output terminal and a 1st TR turned on in response to the data pulse. CONSTITUTION:With a digital signal (P) set to '1', TR T1 is turned on and a TR T6 is turned off, a clock signal phib goes to '1' and then TRs T2, T3 are turned on and a TR T4 is turned off. Then the signals P, phib go both to '1', the TRs T1-T3 are all tuned on and an output Q goes to 0. In this case, the period when the output Q takes 0 depends on the pulse width of the signal phib. The noise attended with a level change is blocked by the TRs T2, T3 in the off state even when the signal (P) 12 (when the TRs T2, T3 are turned off and the TR T4 is turned on) signal phib and the noise does not appear at the output Q. Thus, a wave shaping output C with less noise is obtained.

公开(公告)号：JPH03232313A

公开(公告)日：1991-10-16

申请号：JP2789190

申请日：1990-02-07

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI

IPC: H03K5/08

Abstract: PURPOSE:To make a response at high speed with high accuracy by comparing the first- and second analog voltage while opening-closing the first-, second-, and plural analog switches, and outputting a compared voltage. CONSTITUTION:When analog voltages V1 and V2 are respectively inputted from input terminals 1 and 2 and a control voltage Vc at an L level is applied to a control voltage input terminal 4, all analog switches 3, 12 and 13 are turned to an conductive state and an analog switch 6 is turned to a non-conductive state. Therefore, both voltages at one end T2 of a capacitor 7 and an output end T3 of an inverter 8 become the 1/2 of a power supply voltage VDD. Next, when the control voltage Vc at an H level is impressed to a control voltage input terminal 4, an operation reverse to the above mentioned operation is executed. Thus, the potential of a connecting point T4 comes to the 1/2 of the potential VDD when short-circuiting the input/output of the inverter, and spike noise can be prevented from being generated when opening/closing the analog switch 12.

公开(公告)号：JPH01228223A

公开(公告)日：1989-09-12

申请号：JP5404688

申请日：1988-03-08

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI

IPC: H03M1/36 ,  H03M1/00

Abstract: PURPOSE:To remarkably reduce the number of comparators by dividing the whole of a reference voltage by an exponential scale, dividing each divided reference voltage equally, and obtaining each partitioned reference voltage. CONSTITUTION:A positive side reference voltage VRH corresponds to an (analog value +2 =2 ), and a central voltage VRM to an (analog value + or - 0). Also, the positive side reference voltage corresponds to an analog value 2, and also, voltage nodes by the exponential scales corresponding to analog values 2 , 2 , 2 , and 2 (=2 ) are provided setting the central voltage VRM as reference, and furthermore, a part between each node is divided equally to 16(=2 =2 ). Thereby, the number of voltage nodes at a positive side goes to 2 X(n-i)=80, then, it goes to 2 X(n-i)=160 at both the positive and a negative sides. Therefore, in case that it is n=9 bits and i=4, the numbers of the reference nodes (P1-Pm) and the comparators (C1-Cm) go to 160.

公开(公告)号：JPH0976694A

公开(公告)日：1997-03-25

申请号：JP23579495

申请日：1995-09-13

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI

IPC: B43L1/04 ,  G06F3/033 ,  G06F3/041 ,  G06F3/048

Abstract: PROBLEM TO BE SOLVED: To provide a magnetic element display device such as an electronic blackboard or the like capable of redisplaying two-dimensional information display of which was carried out in the past. SOLUTION: A recording display part 1 is constituted by arranging a plurality of magnetic display elements 11 wherein different colors are applied to respective N and S poles. A locus of a tip of a recording tool 2 is displayed by those respective magnetic display elements. When a display content is preserved, scanning with a record reproducing head 4 is carried out, a direction of each magnetic display element is read via the head 4, and written in a memory 6 capable of being attached and detached via an input-output control part 7. In that case a positional control part 8 supplies a write address corresponding to a head position to the memory 6. If necessary, two-dimensional information in the memory 6 is read, driving of each magnetic display element based on the read data is carried out by the input and output control part 7 and the head 4, and redisplay of the preserved two-dimensional information is carried out.

公开(公告)号：JPH08148982A

公开(公告)日：1996-06-07

申请号：JP31120994

申请日：1994-11-21

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI

IPC: H03K19/003 ,  H03K17/16 ,  H03K19/096

Abstract: PURPOSE: To provide a semiconductor integrated circuit in which power noise is effectively reduced. CONSTITUTION: An in-chip logic circuit is classified into 6 circuit blocks B0, B1, ..., B5. A clock generating circuit CL generates two kinds of reference clocks ϕ10, ϕ20 being reference signals for all logic circuit operations. Clocks ϕ11-ϕ15 delayed sequentially by delay circuits τ10-τ14 are obtained by the reference clock ϕ10 and clocks ϕ21-ϕ25 delayed sequentially by delay circuits τ20-τ24 are obtained by the reference clock ϕ20 and the circuit blocks B0, B1, ..., B5 are operated at a timing deviated little by little by using the clocks.

公开(公告)号：JPH0574249B2

公开(公告)日：1993-10-18

申请号：JP3490388

申请日：1988-02-17

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI

IPC: H03M1/66 ,  H03M1/00 ,  H03M1/70 ,  H03M1/68

公开(公告)号：JPH04111521A

公开(公告)日：1992-04-13

申请号：JP22918090

申请日：1990-08-30

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M1/10 ,  H03K5/00

Abstract: PURPOSE:To obtain a pulse output of less noise from an output element by interposing a second transistor TR, which is turned on in accordance with a synchronizing pulse narrower than a data pulse, between an output terminal and a first TR turned on in accordance with the data pulse. CONSTITUTION:A first TR T1 turned on in accordance with the data pulse and a second TR T2 turned on in accordance with the synchronizing pulse narrower than the data pulse are connected in series, and the output terminal is connected to the side of the second TR T3 of this series connection line, and the pulse output of small noise synchronized with the turning-on timing of the second TR T3 is taken out from the output terminal on condition that first and second TRs T2 and T3 are turned on together. That is, the noise accompanied with the level change of the data pulse is stopped by the second TR T3 and does not reach the output, terminal because the second TR T3 is interposed in the turning-off state between the first TR. T1 and the output terminal. Thus, a pulse output Q of less noise is obtained from the output terminal.

公开(公告)号：JPH0313005A

公开(公告)日：1991-01-22

申请号：JP14800889

申请日：1989-06-09

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI

IPC: H03G3/12

Abstract: PURPOSE:To eliminate spike noise by using an analog switch provided with a base effect compensation circuit correcting the fluctuation of an impedance between input and output terminals for a 1st switch and using an analog switch not provided with the base effect compensation circuit for a 2nd switch. CONSTITUTION:Analog switches 8, 9 may generate spike noise by providing a base effect compensation circuit 39. Since the analog switches are not connected to an operational amplifier 1, the noise is not inputted to the operational amplifier 1. On the other hand, analog switches 6, 7 connecting to a resistor 2 have no base effect compensation circuit, therefore for impedance is changed by an input voltage Vi. Since the input resistance of the operational amplifier 1 is large, a current flowing to the analog switch 6 is very small. Since the potential fluctuation at a connecting point due to the changeover of the analog switches is less, a fast response is obtained.