公开(公告)号：JP2014107730A

公开(公告)日：2014-06-09

申请号：JP2012259732

申请日：2012-11-28

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MAEJIMA TOSHIO

IPC: H03F3/45

CPC classification number: G01P15/14 ,  G01C19/5776 ,  G01P15/00 ,  H03F3/45183

Abstract: PROBLEM TO BE SOLVED: To improve an S/N ratio of an output signal of an amplifier while avoiding an extension of time required for the output signal of the amplifier to stabilize, when amplifying an output signal of a sensor in the amplifier for later use.SOLUTION: The amplifier with a switchable bandwidth is used to amplify an output signal of a sensor. For example, the amplifier is operated in a wide band for a constant time T after the start of signal input from the sensor to the amplifier following power input, and after that the amplifier is operated in a narrow band.

Abstract translation: 要解决的问题：为了提高放大器的输出信号的S / N比，同时避免放大器的输出信号所需的时间的延长以稳定，当放大放大器中的传感器的输出信号供以后使用时 。解决方案：具有可切换带宽的放大器用于放大传感器的输出信号。 例如，在功率输入之后从传感器输入到放大器的信号开始之后，放大器在宽带中操作恒定时间T，之后放大器在窄带中操作。

公开(公告)号：JP2008166864A

公开(公告)日：2008-07-17

申请号：JP2006350615

申请日：2006-12-26

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MAEJIMA TOSHIO

IPC: H03F3/217

CPC classification number: H03F3/2175

Abstract: PROBLEM TO BE SOLVED: To provide a class-D amplifier capable of preventing the occurrence of folding noise to an audio band during PWM modulation, based on the bit streams and of reproducing high-quality sounds, using a simple configuration.
SOLUTION: A PWM modulator 3 performs the PWM modulation processing of adding first and second input signals and outputting PWM modulated pulses, for which a pulse width is modulated that corresponds to the added result. A shift register 2 delays the bit stream BS0 from a Σ modulator 1, generates the bit streams BS1 and BS2 with the time difference of 1/2 of the cycle of the PWM modulation processing, and supplies them to the PWM modulator 3, as the first and second input signals.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够在PWM调制期间，基于比特流和再现高质量的声音，使用简单的配置来防止对音频频带产生折叠噪声的D类放大器。 解决方案：PWM调制器3执行PWM调制处理，其中添加第一和第二输入信号并输出​​PWM调制脉冲，脉宽调制对应于相加结果。 移位寄存器2从Σ调制器1延迟比特流BS0，以PWM调制处理的周期的1/2的时间差产生比特流BS1和BS2，并将其提供给PWM调制器3，作为 第一和第二输入信号。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007124624A

公开(公告)日：2007-05-17

申请号：JP2006226269

申请日：2006-08-23

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MAEJIMA TOSHIO

IPC: H03F3/217 ,  H03F1/32

Abstract: PROBLEM TO BE SOLVED: To provide a class-D amplifier capable of preventing the occurrence of clipping without generating nonlinear distortion.
SOLUTION: An amplifier 100 outputs digital signals VOp and VOn which are pulsewidth-modulated in accordance with an input analog signal. An input section of the amplifier 100 comprises a switch 130 which attenuates the input analog signal by giving an attenuation command signal SW thereto. A clip prevention controller 200 generates the attenuation command signal to intermittently attenuate the input analog signal by detecting that the digital signal is brought into a clip state or a near-clip state, on the basis of the level of a signal within the amplifier 100.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供能够防止在不产生非线性失真的情况下发生限幅的D类放大器。 解决方案：放大器100输出根据输入的模拟信号进行脉冲宽度调制的数字信号VOp和VOn。 放大器100的输入部分包括开关130，该开关通过向其提供衰减命令信号SW来衰减输入的模拟信号。 剪辑防止控制器200基于放大器100内的信号的电平，通过检测数字信号进入剪辑状态或接近剪辑状态来产生衰减命令信号，以间歇地衰减输入的模拟信号。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005159871A

公开(公告)日：2005-06-16

申请号：JP2003397682

申请日：2003-11-27

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MAEJIMA TOSHIO

IPC: H03F1/00

Abstract: PROBLEM TO BE SOLVED: To provide a pop noise reduction circuit which is capable of reducing pop noise that occurs when powering on or powering off an audio amplifier, and quickly rising and falling.
SOLUTION: The pop noise reduction circuit comprises: an analog/digital (A/D) converter (2a) for providing output data resulting from the A/D conversion of an output signal when powering on or powering off an amplifier (1) for amplifying an audio signal; a control means (2b) for fetching the output data and providing data for imparting to the amplifier (1) a bias voltage for allowing the output signal to be a signal of a frequency equal with or lower than an audible band that cannot be reproduced by a reproducing speaker in the case of reproduction; and a D/A converter (2c) for receiving the data, D/A converting the data and providing them to the amplifier (1) as the bias voltage.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种能够减少在上电或关闭音频放大器时发生的弹跳噪声并且快速上升和下降的弹跳噪声降低电路。 弹奏噪声降低电路包括：模拟/数字（A / D）转换器（2a），用于在上电或断电放大器（1）时提供由输出信号的A / D转换产生的输出数据 ），用于放大音频信号; 一种控制装置（2b），用于取出输出数据并提供用于赋予放大器（1）的偏置电压的数据，该偏置电压允许输出信号为等于或低于无法再现的可听频带的频率的信号 在再现的情况下的再现扬声器; 和用于接收数据的D / A转换器（2c），D / A转换数据并将其提供给放大器（1）作为偏置电压。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004128759A

公开(公告)日：2004-04-22

申请号：JP2002288184

申请日：2002-10-01

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MAEJIMA TOSHIO

IPC: G01R19/165 ,  H03K5/08

Abstract: PROBLEM TO BE SOLVED: To provide a window comparator capable of optionally setting two comparison voltages and operable even at a low power supply voltage.
SOLUTION: The window comparator is configured with a first comparator circuit comprising: a first element 10 to which an input voltage is applied; a second element 12 to which a first reference voltage VH is applied; and a first constant current source 30 whose one terminal is connected to ground and making the sum of currents flowing to the first and second elements constant, and with a second comparator circuit comprising: a third element 24 to which the input voltage is applied; a fourth element 26 to which a second reference voltage VL set to a voltage lower than the first reference voltage is applied; and a second constant current source 32 whose one terminal is connected to ground; and a current mirror circuit to making proportion the sum ofcurrent which flowing to the third and fourth elements for the above-mentioned the current of the second element . A voltage across the second constant current source is used for an output VOUT.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003174357A

公开(公告)日：2003-06-20

申请号：JP2002128890

申请日：2002-04-30

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO ,  TODA AKIHIKO

IPC: H03K5/02 ,  H03K3/012 ,  H03K3/356 ,  H03K17/16 ,  H03K19/0185

Abstract: PROBLEM TO BE SOLVED: To provide a signal level shifting circuit capable of preventing the generation of a through current even when power supply voltage capable of applying an input side signal level is dropped. SOLUTION: A power supply voltage detection circuit DT detects the drop of voltage of a power supply VDDL for applying the signal level of an input signal IN. A switch circuit consisting of an NMOS transistor (TR) TN3 is connected to a current route consisting of PMOS TRs TP1, TP2 (a load circuit part) and NMOS TRs TN1, TN2 (a driving circuit part) in a level shift stage LS1. When the voltage drop of the power supply VDDL is detected, the switch circuit is closed. Even when the voltage of the power supply VDDL is dropped and both the NMOS TRs TN1, TN2 are turned on, the generation of a through current can be effectively suppressed in the level shift stage LS1. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH10247852A

公开(公告)日：1998-09-14

申请号：JP35733197

申请日：1997-12-25

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO

IPC: H03M1/08 ,  H03M3/02

Abstract: PROBLEM TO BE SOLVED: To enhance the degrees of freedom of design by facilitating an analog input level setting at which full scale digital data are obtained and its revision. SOLUTION: This A/D converter is made up of a delta-sigma modulator 21, a data conversion section 22, and a decimation filter 23. A bit stream BS, obtained by the delta sigma modulator 21, is subject to data conversion (weighting) by an optional data conversion value T at the data conversion section 22 and converted into a multi-bit stream DBS. The converted output DBS is given to the decimation filter 23, in which the output DBS is converted into multi-bit digital data Do. An analog input level, at which obtains full scale digital data Do is obtained, is varied optionally by the data conversion value T.

公开(公告)号：JPH09307423A

公开(公告)日：1997-11-28

申请号：JP12196396

申请日：1996-05-16

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO

IPC: H01L27/06 ,  H01L21/8249 ,  H03K19/0185

Abstract: PROBLEM TO BE SOLVED: To provide an LSI(large-scale integrated circuit) containing a level conversion circuit of a simple constitution which can attain the direct connection of outputs of LSIs of different power voltage levels without increasing its power consumption. SOLUTION: In order to directly connect the output of an LSI 2 using a power supply VDD2 of a high voltage level to an LSI 1 using a power supply VDD1 of a low voltage level, a level conversion circuit 13 is prepared between an external terminal IN and an input terminal A of an internal circuit 11 to convert the input signal level. The circuit 13 consists of an N-channel MOS transistor TR QN12 whose drain, source, gate and bulk are connected to the terminal IN, the terminal A, a VDD1 terminal and a ground terminal VSS respectively. The TR QN12 has its gate threshold voltage that is set at 0V when its source potential is equal to the VDD1 and thereby the largest amplitude of the terminal A is suppressed at the VDD1 .

公开(公告)号：JPH0983301A

公开(公告)日：1997-03-28

申请号：JP23055795

申请日：1995-09-07

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO

IPC: H03H19/00 ,  H03M1/12

Abstract: PROBLEM TO BE SOLVED: To apply the filter process to the analog signals of plural channels without increasing the circuit scale. SOLUTION: The integration means Ik and Ik+1 successively carry out the integration processing constituting the filter processing to every channel via the time division control. The integration value storage means Mk to Mk+1 store the integration value signals to show the integration processing results to every channel. A switch means SW functions to store the integration value signals in the means Mk to Mk+1 to show the integration processing results to every channel every time the integration processing is interrupted to every channel and also to initialize the integration processing results of means Ik and Ik+1 . The means SW also functions to supply the integration value signals corresponding to every channel to the means Ik and Ik+1 from the means Mk to Mk+1 every time the integration processing is carried out to every channel and also to supply the analog signals to be integrated to the means Ik and Ik+1 .

公开(公告)号：JPH0974356A

公开(公告)日：1997-03-18

申请号：JP22947295

申请日：1995-09-06

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO

IPC: H03M1/52 ,  H03M3/02

Abstract: PROBLEM TO BE SOLVED: To enable analog/digital(A/D) conversion through higher-order integrating processing without extending a circuit scale. SOLUTION: An integrating means 11 repeatedly executes plural kinds of integrating processing. Integrated value storage means 12... store integrated value signals showing the results of integrating processing each time of integrating processing. A switch means 13 stores the integrated value signal showing the result of integrating processing in the integrated value storage means 12 each time that integrating processing is interrupted, and the integrating means 11 is initialized. Besides, each time integrating processing is executed, the switch means 13 supplies the integrated value signal corresponding to that integrating processing from the integrated value storage means 12 to the integrating means 11 and supplies an analog signal as the processing object of this integrating processing to the integrating means 11. Further, when this integrating processing includes the result of the other integrating processing as a processing object, the integrated value signal corresponding to the other integrating processing is supplied from the integrated value storage means 12 to the integrating means 11.