Abstract:
An amplifier circuit (100) includes an output terminal (Po), an amplification unit (A1) and a switch (T3). The output terminal (Po) is used to output an amplification signal (Sa). The amplification unit (A1) includes a first transistor (T1) and a second transistor (T2). The first transistor (T1) includes a control terminal for receiving a first input signal (S1), a first terminal coupled to the output terminal (Po) for outputting an amplified first input signal, and a second terminal. The second transistor (T2) includes a control terminal for receiving a second input signal (S2), a first terminal coupled to the output terminal (Po) for outputting an amplified second input signal, and a second terminal. The switch (T3) includes a terminal coupled to the second terminal of the first transistor (T1). The amplification signal (Sa) is generated using at least the amplified first input signal and/or the amplified second input signal.
Abstract:
A control circuit (100) with a bypass function includes a first signal terminal (N1), a second signal terminal (N2), an output terminal (N opt ), a first switch unit (110) to a third switch unit (130), an output switch unit (150) and a bypass unit (180). The first signal terminal (N1) is used for receiving a first signal (S1). The second signal terminal (N2) is used for receiving a second signal (S2). The first switch unit (110) is coupled to the first signal terminal (N1). The second switch unit (120) is coupled between the first switch unit (110) and the output switch unit (150). The third switch unit (130) is coupled to the second signal terminal (N2). The output switch unit (150) is coupled between the second switch unit (120) and the output terminal (N opt ). The bypass unit (180) is coupled between the first switch unit (110) and the output terminal (N opt ).
Abstract:
A voltage control device (100) includes a charge pump (110), a driving circuit (120), and a control circuit (130). The charge pump (110) provides a first voltage (V1). The driving circuit (120) is coupled to the charge pump (110), and receives the first voltage (V1) and a reference voltage (VG). The driving circuit (120) outputs a driving signal (SIG OUT ) according to an input signal (SIG IN ), the first voltage (V1) and the reference voltage (VG). The control circuit (130) is coupled to the charge pump (110) and the driving circuit (120). Before the first voltage (V1) reaches a threshold level (THV1), the control circuit (130) adjusts the reference voltage (VG) to increase the voltage gap between the first voltage (V1) and the reference voltage (VG).
Abstract:
A motion sensing method includes monitoring for a first motion in a first region (210, 1010, 1110, 1210, 1310, 1410, 1510, 1610, 1710) using a first antenna (310, 680, 780, 880, 980, 1080, 1180, 1280, 1380, 1480, 1580, 1680, 1780) using a first motion detection parameter, when no first motion is sensed by the monitoring using the first antenna (310, 680, 780, 880, 980, 1080, 1180, 1280, 1380, 1480, 1580, 1680, 1780), monitoring for a second motion in a second region (220, 1020, 1120, 1220, 1320, 1420, 1520, 1620, 1720) using a second antenna (320, 690, 790, 890, 990, 1090, 1190, 1290, 1390, 1490, 1590, 1690, 1790) using a second motion detection parameter, and when no second motion is sensed by monitoring using the second antenna (320, 690, 790, 890, 990, 1090, 1190, 1290, 1390, 1490, 1590, 1690, 1790), designating a space, which encompasses the second region (220, 1020, 1120, 1220, 1320, 1420, 1520, 1620, 1720), as unoccupied, wherein the first region (210, 1010, 1110, 1210, 1310, 1410, 1510, 1610, 1710) and the second region (220, 1020, 1120, 1220, 1320, 1420, 1520, 1620, 1720) overlap one another, and the first motion detection parameter is different from the second motion detection parameter.
Abstract:
A subsampling motion detector(100, 150, 200, 300) configured to detect motion information of an object (24) under measurement receives a first wireless radio frequency (RF) signal and transmits a second wireless RF signal, the first wireless RF signal being generated by reflecting the second wireless RF signal from the object (24). A controllable oscillator (18, 58) outputs an oscillation signal, wherein the first wireless RF signal is injected to the controllable oscillator (18, 58) for controlling the controllable oscillator (18, 58) through injecting locking. The subsampling motion detector (100, 150, 200, 300) further includes a subsampling phase detector (SSPD) (12, 112, 202) generating a control signal according to the oscillation signal generated by the controllable oscillator (18, 58) and a reference frequency (fXTAL), the SSPD outputting the control signal to the controllable oscillator (18, 58) for controlling the controllable oscillator (18, 58), the oscillation signal of the controllable oscillator (18, 58) being locked to a multiple of the reference frequency (fXAL) and the control signal representing the motion information of the object (24).
Abstract:
A voltage regulator (30) includes an amplifier (310), a power device (320), a delay signal generator (340), and a voltage-generating circuit (330). The amplifier (310) generates a control signal according to a reference voltage and a feedback voltage. The power device (320) generates the output voltage by regulating the output current according to the switch control signal. The delay signal generator (340) generates a plurality of sequential delay signals each having distinct delay time with respect to an externally applied power-on burst signal. The voltage-generating circuit (330) provides an equivalent resistance for generating the feedback voltage corresponding to the output voltage, and regulates the output voltage by adjusting the equivalent resistance according to the plurality of sequential delay signals.
Abstract:
A detector (200) includes an oscillation source (210), a frequency multiplier (220), a transceiver (230) and a demodulator (240). The oscillation source (210) generates a first injection signal (Vi1) with a first frequency (f1). The frequency multiplier (220) receives the first injection signal (Vi1), outputs an output signal (Vo) and receives a second injection signal (Vi2) with a second frequency (f2). The frequency multiplier (220) uses injection locking to lock a frequency of the output signal (Vo) at a multiple of the first frequency (f1), and uses injection pulling to pull the frequency of the output signal (Vo) to the second frequency (f2). The transceiver (230) transmits the output signal (Vo) and receives a received signal (Vrx) with a third frequency (f3) for updating the second injection signal (Vi2). The demodulator (240) performs a demodulation operation according to the output signal (Vo) so as to generate a displacement signal (Vd).
Abstract:
A detector (200) includes an oscillation source (210), a frequency multiplier (220), a transceiver (230) and a demodulator (240). The oscillation source (210) generates a first injection signal (Vi1) with a first frequency (f1). The frequency multiplier (220) receives the first injection signal (Vi1), outputs an output signal (Vo) and receives a second injection signal (Vi2) with a second frequency (f2). The frequency multiplier (220) uses injection locking to lock a frequency of the output signal (Vo) at a multiple of the first frequency (f1), and uses injection pulling to pull the frequency of the output signal (Vo) to the second frequency (f2). The transceiver (230) transmits the output signal (Vo) and receives a received signal (Vrx) with a third frequency (f3) for updating the second injection signal (Vi2). The demodulator (240) performs a demodulation operation according to the output signal (Vo) so as to generate a displacement signal (Vd).
Abstract:
A digital phase-locked loop having a phase frequency detector (PFD), a 3-state phase frequency detection converter (3-state PFD converter), a loop filter and a digital voltage-controlled oscillator is provided. The PFD receives an input frequency and a reference frequency and outputs a first signal and a second signal based on the phase difference between the input frequency and the reference frequency. The 3-state PFD converter outputs a 3-state signal according to the first and second signals, wherein the 3-state signal is presented in 1, 0 and -I. The loop filter outputs at least one control bit based on only the 3-state signal. The DCO adjusts the outputted oscillation frequency according to the control bit.
Abstract:
An auxiliary voltage generating unit (200) for a radio frequency switch (100) includes a first input and a second input respectively configured to receive a first control signal and a second control signal, characterized in that the first control signal and the second control signal are configured to control which one of a plurality of paths in the radio frequency switch (100) is enabled, and at least one output, configured to output an auxiliary voltage, derived from at least one of the first control signal or the second control signal, that is used to operate the radio frequency switch (100). The auxiliary voltage may be a bias voltage and/or a voltage used to power an inverter (150) used to enable a selected branch as an isolation branch or shunt branch.