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公开(公告)号：US09929701B1
公开(公告)日：2018-03-27
申请号：US15272103
申请日：2016-09-21
Applicant: Peregrine Semiconductor Corporation
Inventor： Hossein Noori , Chih-Chieh Cheng
CPC classification number: H03F1/3205 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/18 , H03F2200/21 , H03F2200/211 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/24 , H03F2200/243 , H03F2200/249 , H03F2200/27 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/312 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/417 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/495 , H03F2200/546 , H03F2200/72 , H03F2200/75 , H03G1/0029 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G3/008 , H03G3/10 , H03G2201/106 , H03G2201/307 , H03G2201/504
Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
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公开(公告)号：US20170317651A1
公开(公告)日：2017-11-02
申请号：US15528934
申请日：2015-11-02
Applicant: ICEpower a/s
Inventor： Kennet Skov Andersen
CPC classification number: H03F1/305 , H03F1/02 , H03F3/183 , H03F3/187 , H03F3/217 , H03F3/2173 , H03F2200/03 , H03F2200/129 , H03F2200/135 , H03F2200/144 , H03F2200/156 , H03F2200/258 , H03F2200/342 , H03F2200/426 , H03F2200/441 , H03F2200/444 , H03F2200/66 , H03F2200/78 , H03G3/301 , H03G3/348 , H03G2201/106
Abstract: A close-down pop reduction system and a method for close-down pop reduction in an audio amplifier assembly are disclosed. The switching power conversion system comprises a forward path having a compensator and a switching power stage and a signal path from an output of a comparator in the switching power stage to a sequence control unit. The signal path includes a close-down timing circuit configured to provide a timing signal. The sequence control unit is configured to eliminate the input signal, increase the switch frequency of the close-down pop reduction system and disable the switching power stage at a moment in time within a PWM pulse of the switching power stage. Hereby, it is e.g. possible to minimize the audible pop during close-down of audio amplifier assemblies.
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公开(公告)号：US20170064447A1
公开(公告)日：2017-03-02
申请号：US15246373
申请日：2016-08-24
Applicant: Red Lion 49 Limited
Inventor： David Joseph Mate
CPC classification number: H04R3/04 , H03F3/187 , H03F3/45071 , H03F3/45475 , H03F2200/03 , H03F2200/165 , H03F2200/321 , H03F2203/45576 , H03F2203/45614 , H03G1/0005 , H03G1/0088 , H03G2201/106 , H03H11/245
Abstract: Apparatus (301) for switchable attenuation of a differential input signal from a microphone includes positive and negative non-attenuating paths (406, 410) have n- and p-type MOSFETs (421, 422, 423, 424) in back-to-back configurations; positive and negative attenuating paths (405, 409) have n- and p-type MOSFETs (415, 416, 418, 419) in back-to-back configurations in combination with resistors; a gate driver (425) applies a drive signal of one polarity (QNEG) to gates of the n-type MOSFETs in the attenuating paths and the p-type MOSFETs in the non-attenuating paths, and a drive signal of opposite polarity (QPOS) to the gates of the p-type MOSFETs in the attenuating paths and the n-type MOSFETs in the non-attenuating paths; and the state of the MOSFETs depends on the drive signals at their gates, and thus the input signal may be routed via either the non-attenuating paths or the attenuating paths by controlling the drive signals.
Abstract translation: 用于来自麦克风的差分输入信号的可切换衰减的装置（301）包括正和负非衰减路径（406,410），所述正衰减路径和负非衰减路径具有背对着的n型和p型MOSFET（421,422,423,424） 后退配置; 正和负衰减路径（405,409）具有背对背配置的n型和p型MOSFET（415,416,418,419），与电阻器组合; 栅极驱动器（425）将衰减路径中的n型MOSFET的栅极和非衰减路径中的p型MOSFET施加一个极性的驱动信号（QNEG）和相反极性的驱动信号（QPOS ）到衰减路径中的p型MOSFET的栅极和非衰减路径中的n型MOSFET; 并且MOSFET的状态取决于其栅极处的驱动信号，因此通过控制驱动信号可以通过非衰减路径或衰减路径来路由输入信号。
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44.发明授权公开(公告)号：US09374051B2
公开(公告)日：2016-06-21
申请号：US14728196
申请日：2015-06-02
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Abdulrhman M. S Ahmed , Mario M. Bokatius , Paul R. Hart , Joseph Staudinger , Richard E. Sweeney
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
Abstract translation: 与包括多个放大器路径的放大器一起使用的电路的实施例包括与第一电路并联的第一电路和第二电路。 第一电路包括耦合到第一功率分配器输出的第一输入，耦合到多个放大器路径的第一放大器路径的第一输出以及耦合在第一输入和第一输出之间的第一可调移相器和第一衰减器串联 。 第二电路包括耦合到第二功率分配器输出的第二输入，耦合到多个放大器路径的第二放大器路径的第二输出以及耦合在第二输入和第二输出之间的第二可调相移器。
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45.发明申请公开(公告)号：US20150280665A1
公开(公告)日：2015-10-01
申请号：US14728196
申请日：2015-06-02
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： ABDULRHMAN M. S AHMED , MARIO M. BOKATIUS , PAUL R. HART , JOSEPH STAUDINGER , RICHARD E. SWEENEY
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
Abstract translation: 与包括多个放大器路径的放大器一起使用的电路的实施例包括与第一电路并联的第一电路和第二电路。 第一电路包括耦合到第一功率分配器输出的第一输入，耦合到多个放大器路径的第一放大器路径的第一输出以及耦合在第一输入和第一输出之间的第一可调移相器和第一衰减器串联 。 第二电路包括耦合到第二功率分配器输出的第二输入，耦合到多个放大器路径的第二放大器路径的第二输出以及耦合在第二输入和第二输出之间的第二可调相移器。
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Patent Agency Ranking
公开(公告)号：US20130194023A1
公开(公告)日：2013-08-01
申请号：US13360473
申请日：2012-01-27
Applicant: Abdulrhman M.S Ahmed , Mario M. Bokatius , Paul R. Hart , Joseph Staudinger , Richard E. Sweeney
Inventor： Abdulrhman M.S Ahmed , Mario M. Bokatius , Paul R. Hart , Joseph Staudinger , Richard E. Sweeney
IPC: G06F7/44
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; and a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output.
Abstract translation: 可调功率分配器包括：具有输入的功率分配器和第一和第二分频器输出; 第一可调移相器和第一可调衰减器串联耦合到第一分频器输出并提供第一功率输出; 以及耦合到第二分频器输出并提供第二功率输出的第二可调移相器和第二可调衰减器系列。
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47.发明申请公开(公告)号：US20050242875A1
公开(公告)日：2005-11-03
申请号：US11081384
申请日：2005-03-16
Applicant: Mark Gurvich , Ahmad Khanifar , Nikolai Maslennikov , Alexander Rabinovich
Inventor： Mark Gurvich , Ahmad Khanifar , Nikolai Maslennikov , Alexander Rabinovich
CPC classification number: H03F1/32 , H03F1/0211 , H03F1/0222 , H03F1/0244 , H03G3/3042 , H03G2201/106 , H03G2201/206 , H03G2201/307
Abstract: A high efficiency radio frequency (RF) power amplifier having dynamically controlled back off is disclosed. The RF input voltage is sampled by an adaptive analog signal processing circuit. The adaptive analog signal processing circuit controls the supply voltage to RF amplifier devices, such as LDMOS devices, which varies the efficiency or back off of the power amplifier. The variable supply voltage in turn varies peak power of the amplifier.
Abstract translation: 公开了具有动态控制的退避的高效率射频（RF）功率放大器。 RF输入电压由自适应模拟信号处理电路采样。 自适应模拟信号处理电路控制对诸如LDMOS器件的RF放大器器件的电源电压，这些器件改变功率放大器的效率或退避。 可变电源电压又会改变放大器的峰值功率。
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公开(公告)号：JP2018078390A
公开(公告)日：2018-05-17
申请号：JP2016217462
申请日：2016-11-07
Applicant: 富士通株式会社
Inventor： 志村 利宏
CPC classification number: H03H11/16 , H03F3/45475 , H03F2200/06 , H03F2200/09 , H03F2203/45171 , H03F2203/45621 , H03F2203/45731 , H03G1/0088 , H03G3/30 , H03G2201/106 , H03H11/20
Abstract: 【課題】従来よりも損失の小さい位相切り替え機能付き可変増幅装置を提供する。 【解決手段】位相切り替え機能付き可変増幅装置は、1系統の入力端と2系統の出力端とを有し、1系統の入力端に入力されるシングルエンド信号の出力先を切り替えるスイッチ部と、スイッチ部の2系統の出力端の各々に接続され、シングルエンド信号を互いに位相が180°異なる一対の差動信号に変換し且つスイッチ部における切り替え動作に応じて一対の差動信号の位相を反転させる第1の変換部と、一対の差動信号を制御電圧に応じた増幅量で増幅させて出力する可変増幅部と、可変増幅部から出力された一対の差動信号をシングルエンド信号に変換する第2の変換部と、を含む。 【選択図】図3
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公开(公告)号：JP2018014543A
公开(公告)日：2018-01-25
申请号：JP2014240808
申请日：2014-11-28
Applicant: ソニー株式会社
CPC classification number: H03F1/26 , H03F1/223 , H03F3/193 , H03F3/211 , H03F3/3022 , H03F3/68 , H03F2200/294 , H03F2200/372 , H03F2200/451 , H03G1/0088 , H03G1/0094 , H03G2201/106
Abstract: 【課題】出力信号のS/N比を劣化させることなく一方のパスに設けた増幅器からのノイズ成分が出力信号から実質的に無くなるように構成可能とする。 【解決手段】入力ノードN1に接続されて第1中間信号を生成する第1増幅器Ap1と、第1中間信号を入力ノードに帰還させる帰還抵抗Rfと、第1中間信号を受け取って第2中間信号S10を生成する減衰器Atと、入力ノードに接続されて第3中間信号S21を生成する第2増幅器Ap2と、入力ノードに接続されて第4中間信号S22を生成する第3増幅器Ap3と、第2中間信号と第3中間信号と第4中間信号とを用いて出力信号Soutを生成する加算器30と、を備えた。 【選択図】図1
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公开(公告)号：JP2018078391A
公开(公告)日：2018-05-17
申请号：JP2016217463
申请日：2016-11-07
Applicant: 富士通株式会社
Inventor： 志村 利宏
CPC classification number: H03G1/007 , G01R31/025 , G01R31/31926 , H01P1/15 , H01P1/18 , H01P1/22 , H03G1/0088 , H03G2201/106 , H03H7/20 , H03H11/20 , H03H11/245 , H04L27/22
Abstract: 【課題】従来よりも高アッテネーションを実現できる可変減衰装置を提供する。 【解決手段】可変減衰装置は、互いに位相が180°異なる一対の差動信号の一方が第1の入力端に入力され、第1の入力端に入力された信号を制御電圧に応じた減衰量で減衰させて第1の出力端から出力する第1の可変減衰部と、一対の差動信号の他方が第2の入力端に入力され、第2の入力端に入力された信号を制御電圧に応じた減衰量で減衰させて第2の出力端から出力する第2の可変減衰部と、第2の入力端に入力された信号を第1の出力端に分配する第1の信号分配部と、第1の入力端に入力された信号を第2の出力端に分配する第2の信号分配部と、を含む。 【選択図】図4
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