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公开(公告)号：CA2108851A1
公开(公告)日：1995-03-11
申请号：CA2108851
申请日：1993-10-20
Applicant: ATI TECHNOLOGIES INC
Inventor： LUM SANFORD S
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公开(公告)号：CA2102032A1
公开(公告)日：1995-03-11
申请号：CA2102032
申请日：1993-10-29
Applicant: ATI TECHNOLOGIES INC
Inventor： LUM SANFORD S
Abstract: Enhancing each pixel of a digital color video image by, for each component part of a source pixel, successively adding a truncation error of an immediately preceding previous pixel in an X direction to a current pixel. A resulting value is truncated to form a truncation error and most significant bits, and the most significant bits are provided to a destination line.
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公开(公告)号：CA2060039A1
公开(公告)日：1993-07-25
申请号：CA2060039
申请日：1992-01-24
Applicant: ATI TECHNOLOGIES INC
Inventor： HARTOG ADRIAN H , DAVIES ROBIN E R
Abstract: A method for drawing lines on a graphics device in such manner in that only those points lying inside a specified rectangular area of the device are drawn. Predetermined digital outcodes are generated for defining the endpoints of the lines and a decision is made whether to draw or not draw the lines based on the relationship of the endpoints with respect to both the specified rectangular area of the device, and a second larger rectangular area of the device.
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公开(公告)号：AU2011200479B2
公开(公告)日：2013-08-29
申请号：AU2011200479
申请日：2011-02-04
Applicant: ATI TECHNOLOGIES INC
Inventor： MOREIN STEVEN , LEFEBVRE LAURENT , GRUBER ANDY , SKENDE ANDI
Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer. VERTEX VERTEX TO MUX FETCH CACHE FROM MUX MEMORY 0 INSTRUCTION 8 63 CONSTANTS -94 E. r-95 97 SOURCE A SOURCE B SOURCES \93
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公开(公告)号：ZA200705692B
公开(公告)日：2008-08-27
申请号：ZA200705692
申请日：2007-07-11
Applicant: ATI TECHNOLOGIES INC
Inventor： STEVEN MOREIN , LAURENT LEFEBVRE , ANDY GRUBER , ANDI SKENDE
Abstract: A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.
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Patent Agency Ranking
公开(公告)号：DE60321612D1
公开(公告)日：2008-07-31
申请号：DE60321612
申请日：2003-02-10
Applicant: ATI TECHNOLOGIES INC , ELPIDA MEMORY INC
Inventor： MACRI JOSEPH , DRAPKIN OLEG , TEMKINE GRIGORI , NAGASHIMA OSAMU
IPC: G11C7/10 , G11C11/4096
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公开(公告)号：ZA200605069B
公开(公告)日：2008-06-25
申请号：ZA200605069
申请日：2006-11-19
Applicant: ATI TECHNOLOGIES INC
Inventor： MOREIN STEVEN , LEFEBVRE LAURENT , GRUBER ANDY , SKENDE ANDI
Abstract: A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.
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公开(公告)号：DE69934465D1
公开(公告)日：2007-02-01
申请号：DE69934465
申请日：1999-09-14
Applicant: ATI TECHNOLOGIES INC , ATI INT SRL
Inventor： RAKIB SELIM SHLOMO , BERNSTEIN ZVI
Abstract: A method and apparatus for interleaving symbols from a one dimensional TDMA 802.14 or MCNS minislot or other TDMA stream into two dimensional arrays in code and time for transmission on a code division multiplexed digital data transmission system. There are two methods disclosed. The first calculates i and j values for storage in RAM as a function of the symbol index in the TDMA stream, the number of codes to be employed, the column space design parameter representing the number of columns in the array, i.e., symbol times, that could be adversely affected by burst noise, and a calculated total number of columns in the array. The result is an array in which no indices of two symbols within any column or between columns of the column space are closer together than a design parameter vertical distance. The other method is similar but interleaves on both a column space as well as a row space so as to spread out the effects of both burst noise and intercode interference so that any errors that result are within the range of the redundant ECC bits to detect and correct.
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公开(公告)号：CA2192532C
公开(公告)日：2007-01-23
申请号：CA2192532
申请日：1996-12-10
Applicant: ATI TECHNOLOGIES INC
Inventor： LEONE PASQUALE
Abstract: A software/hardware hybrid video decoder, particularly suited for decoding MPEG video, that takes advantage of processing capabilities of graphics coprocessors to perform the motion compensation portion of video decoding. Motion compensation is performed by bit block transfer (bit BLT) operations on the graphics coprocessor. The bit BLT operations perform the addition of pixels in the reference and error blocks. Bit BLT operations may also be used for interpolation between reference blocks to provide subpixel resolution for motion vectors.
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公开(公告)号：CA2133617C
公开(公告)日：1999-03-30
申请号：CA2133617
申请日：1994-10-04
Applicant: ATI TECHNOLOGIES INC
Inventor： YANG IVAN WONG YIN
Abstract: A method of communicating with peripheral devices via a personal computer parallel port having computer data bus lines but no address bus lines comprising connecting the input of a multiplexer to the parallel port, the multiplexer having a data bus input and a databus output and an address bus output, applying address data to the computer data bus, applying an address control signal to the multiplexer and passing the address data only to the address bus output as a result thereof.
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