公开(公告)号：CA2585860C

公开(公告)日：2014-10-28

申请号：CA2585860

申请日：2004-11-19

Applicant: ATI TECHNOLOGIES INC

Inventor： MOREIN STEVEN ,  LEFEBVRE LAURENT ,  GRUBER ANDY ,  SKENDE ANDI

IPC: G06T15/80 ,  G06T15/00

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

公开(公告)号：AU2004292018A1

公开(公告)日：2005-06-02

申请号：AU2004292018

申请日：2004-11-19

Applicant: ATI TECHNOLOGIES INC

Inventor： GRUBER ANDY ,  LEFEBVRE LAURENT ,  SKENDE ANDI ,  MOREIN STEVEN

IPC: G06T15/00 ,  G06T15/80

Abstract: A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.

公开(公告)号：AU2011200479A1

公开(公告)日：2011-02-24

申请号：AU2011200479

申请日：2011-02-04

Applicant: ATI TECHNOLOGIES INC

Inventor： MOREIN STEVEN ,  LEFEBVRE LAURENT ,  GRUBER ANDY ,  SKENDE ANDI

IPC: G06T15/00 ,  G06T15/50 ,  G06T15/80

Abstract: A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.

公开(公告)号：CA2585860A1

公开(公告)日：2006-06-02

申请号：CA2585860

申请日：2004-11-19

Applicant: ATI TECHNOLOGIES INC

Inventor： MOREIN STEVEN ,  LEFEBVRE LAURENT ,  GRUBER ANDY ,  SKENDE ANDI

IPC: G06T15/00 ,  G06T15/80

Abstract: A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.

公开(公告)号：AU2004292018B2

公开(公告)日：2010-11-11

申请号：AU2004292018

申请日：2004-11-19

Applicant: ATI TECHNOLOGIES INC

Inventor： GRUBER ANDY ,  LEFEBVRE LAURENT ,  SKENDE ANDI ,  MOREIN STEVEN

IPC: G06T15/00 ,  G06T15/80

Abstract: A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.

公开(公告)号：HK1099111A1

公开(公告)日：2007-08-03

申请号：HK07103641

申请日：2007-04-04

Applicant: ATI TECHNOLOGIES INC

Inventor： MOREIN STEVEN ,  LEFEBVRE LAURENT ,  GRUBER ANDY ,  SKENDE ANDI

IPC: G06T15/00 ,  G06T15/80

Abstract: A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.

公开(公告)号：AU2011200479B2

公开(公告)日：2013-08-29

申请号：AU2011200479

申请日：2011-02-04

Applicant: ATI TECHNOLOGIES INC

Inventor： MOREIN STEVEN ,  LEFEBVRE LAURENT ,  GRUBER ANDY ,  SKENDE ANDI

IPC: G06T15/00 ,  G06T15/50 ,  G06T15/80

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer. VERTEX VERTEX TO MUX FETCH CACHE FROM MUX MEMORY 0 INSTRUCTION 8 63 CONSTANTS -94 E. r-95 97 SOURCE A SOURCE B SOURCES \93

公开(公告)号：ZA200605069B

公开(公告)日：2008-06-25

申请号：ZA200605069

申请日：2006-11-19

Applicant: ATI TECHNOLOGIES INC

Inventor： MOREIN STEVEN ,  LEFEBVRE LAURENT ,  GRUBER ANDY ,  SKENDE ANDI

IPC: G06T15/00 ,  G06T15/80

Abstract: A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.