-
公开(公告)号：US20230209811A1
公开(公告)日：2023-06-29
申请号：US18177076
申请日：2023-03-01
Inventor： Guangsu SHAO , Deyuan XIAO , Weiping BAI , Yunsong QIU
IPC: H10B12/00
CPC classification number: H10B12/482 , H10B12/05 , H10B12/315
Abstract: A method for manufacturing a semiconductor structure includes: forming first shallow trench isolation structures in a substrate, which isolate a plurality of active areas extending in first direction in the substrate, in which a first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer stacked from bottom up in sequence; forming a plurality of word line isolation grooves in the substrate, in which a word line isolation groove is located above the sacrificial layer and extends in second direction; forming a second dielectric layer on sidewalls of the word line isolation groove, in which a pore penetrating to the substrate is provided inside the second dielectric layer; metallizing a lower part of an active area based on the pore to form a bit line extending in first direction; and removing the sacrificial layer based on the pore to form an air gap between adjacent bit lines.
-
公开(公告)号：US20230180457A1
公开(公告)日：2023-06-08
申请号：US18162997
申请日：2023-02-01
Inventor： Mengmeng YANG , Xiaoling WANG
IPC: H10B12/00
CPC classification number: H10B12/31 , H10B12/033
Abstract: A method for forming a capacitor includes: providing a substrate; sequentially forming a first sacrificial layer and a first support layer for covering the substrate; forming first openings penetrating through the first support layer; sequentially forming a second sacrificial layer and a second support layer for covering a remaining portion of the first support layer; forming through holes which sequentially penetrate through the second support layer, the second sacrificial layer, the remaining portion of the first support layer, and the first sacrificial layer; forming first electrode layers, each first electrode layer covering an inner wall of a respective one of the through holes; forming second openings penetrating through a remaining portion of the second support layer; and sequentially forming a dielectric layer and a second electrode layer for covering the first electrode layers, to form the capacitor.
-
公开(公告)号：US20230172072A1
公开(公告)日：2023-06-01
申请号：US17827778
申请日：2022-05-29
Inventor： Xiaoguang WANG , Huihui LI , Wei CHANG , Kanyu CAO
CPC classification number: H01L43/08 , H01L27/226 , H01L43/02 , H01L43/12
Abstract: Embodiments provide a layout and a processing method thereof, a storage medium and a program product. The layout has a first memory area and a second memory area. The layout includes a base substrate array pattern and a storage pattern, the base substrate array pattern includes a plurality of plug patterns spaced apart; and the storage pattern includes a magnetic tunnel junction pattern in the first memory area and a capacitor pattern in the second memory area. The magnetic tunnel junction pattern shares a partially overlapped area with a given one of the plurality of plug patterns in the first memory area, and the capacitor pattern shares a partially overlapped area with a given one of the plurality of plug patterns in the second memory area.
-
公开(公告)号：US20230171971A1
公开(公告)日：2023-06-01
申请号：US17853877
申请日：2022-06-29
Inventor： Xiaoguang WANG , Huihui LI , Qiang ZHANG , Minmin WU , Shan WANG
IPC: H01L27/105
CPC classification number: H01L27/1052
Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate including a first array region and a second array region. The first array region is provided with a first memory array comprising a plurality of first memory structures, and the second array region is provided with a second memory array comprising a plurality of second memory structures. Compared with related technologies where different memory structures are stacked on a substrate, in this embodiment, the plurality of first memory structures and the plurality of second memory structures are arranged side by side on the substrate, which is advantageous to simplifying fabrication processes and improving production efficiency.
-
公开(公告)号：US20230171952A1
公开(公告)日：2023-06-01
申请号：US17814271
申请日：2022-07-22
Inventor： Deyuan XIAO , Guangsu SHAO
IPC: H01L27/108 , G11C5/06
CPC classification number: H01L27/10841 , H01L27/10814 , H01L27/10864 , H01L27/10867 , H01L27/1087 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10897 , G11C5/063
Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: an array region, where the array region is provided with a plurality of active pillars; a plurality of bit lines extending along a first direction, where the bit line is located at a bottom of the active pillar; and a plurality of word lines extending along a second direction, where any one of the word lines covers sidewalls of a column of the active pillars arranged along the second direction; and the first direction and the second direction form a predetermined angle, and the predetermined angle is an acute angle or an obtuse angle.
-
Patent Agency Ranking
公开(公告)号：US11626558B2
公开(公告)日：2023-04-11
申请号：US17812549
申请日：2022-07-14
Inventor： Xiaoguang Wang , Dinggui Zeng , Huihui Li , Kanyu Cao
IPC: H01L43/08 , H01L27/22 , H01L43/02 , H01L29/786 , H01L23/528 , H01L29/423 , H01L43/12
Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a plurality of transistors arranged in a staggered manner, wherein the transistors share one source plate, a channel of the transistor is located on the source plate, and a channel length direction of the transistor is perpendicular to a surface of the source plate, and a material of the channel includes an oxide semiconductor; a plurality of drain contact members, electrically connected to drains of the transistors, wherein an odd number of transistors share one drain contact member, and the transistors sharing the same drain contact member are driven by a same word line; and a plurality of magnetic tunnel junctions, located on the drain contact members, wherein the magnetic tunnel junctions are electrically connected to the drain contact members in a one-to-one corresponding manner.
-
公开(公告)号：US20230064849A1
公开(公告)日：2023-03-02
申请号：US17845113
申请日：2022-06-21
IPC: H01L27/108 , H01L49/02
Abstract: A semiconductor structure includes a substrate, a storage capacitor unit, a transistor, and an electrical connection structure. The storage capacitor unit is located at an array area and includes: N insulation posts, distributed in a direction parallel to a surface of the substrate; a bottom electrode layer; a top electrode layer, directly facing the bottom electrode layer; and a capacitor dielectric layer, located between the top and bottom electrode layers. One of the bottom or top electrode layers corresponding to the N insulation posts is a continuous film layer, and the other is discrete film layers. The transistor is located at a circuit area and includes a capacitor control terminal located in the substrate of the circuit area. The electrical connection structure is electrically connected to the capacitor control terminal, and extends from the circuit area to the array area to come into contact with a corresponding discrete film layer.
-
公开(公告)号：US20230063571A1
公开(公告)日：2023-03-02
申请号：US17848895
申请日：2022-06-24
Inventor： Guangsu SHAO , Mengkang Yu , Xingsong Su
IPC: H01L27/108
Abstract: A method for forming a capacitor, the capacitor and a semiconductor device are provided. The method includes: providing a semiconductor structure including a substrate, a stacked-layer structure, a protective layer, a first mask layer, and a photolithography layer which is provided with a plurality of cross-shaped patterns arranged in a square close-packed manner; patterning the first mask layer based on the photolithography layer; forming a plurality of through holes penetrating through the protective layer and the stacked-layer structure based on the patterned first mask layer by etching, in which in a direction perpendicular to a surface of the substrate, a projection of each through hole is cross-shaped, and the plurality of through holes are arranged in the square close-packed manner; and forming a first electrode layer, a dielectric layer and a second electrode layer covering an inner wall of each through hole to form the capacitor.
-
公开(公告)号：US20230063473A1
公开(公告)日：2023-03-02
申请号：US17750458
申请日：2022-05-23
Inventor： Guangsu SHAO , Deyuan XIAO , Yunsong QIU
IPC: H01L21/762 , H01L21/768 , H01L21/304
Abstract: Provided is a method for manufacturing a semiconductor structure. It includes: forming first grooves filled with a first dielectric layer and extending in a first direction in a substrate; forming second grooves extending in a second direction in the substrate and the first dielectric layer, the second grooves and the first grooves being intersected and defining discrete active columns in the substrate; depositing second dielectric layers on sidewalls of the second grooves; depositing sacrificial layers in the second grooves, the sacrificial layers being sandwiched between the second dielectric layers; removing part of the first dielectric layer and part of the second dielectric layer, and forming hole structures extending in the second direction, the hole structures surrounding the active columns, and adjacent hole structures being separated by the sacrificial layers; forming word lines in the hole structures; and removing the sacrificial layers to form air gaps between adjacent word lines.
-
60.发明申请公开(公告)号：US20230061322A1
公开(公告)日：2023-03-02
申请号：US17805004
申请日：2022-06-01
Inventor： Xiaoguang WANG , Huihui LI , DINGGUI ZENG , Jiefang DENG , Kanyu CAO
Abstract: A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming an MTJ structure and a first mask structure in sequence on the substrate; performing a patterning process on the first mask structure to form a first pattern extending in a first direction; transferring the first pattern to the MTJ structure; forming a second mask structure on the MTJ structure; performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction and being not perpendicular to the second direction; and performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.
-
-
-
-
-
-
-
-
-
Search Results
108
records
(took 0.031 seconds)
