公开(公告)号：US20030107924A1

公开(公告)日：2003-06-12

申请号：US10319511

申请日：2002-12-16

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Hiroyuki Mizuno ,  Takao Watanabe ,  Mitsuru Hiraki ,  Hitoshi Tanaka

IPC: G11C005/00

CPC classification number: G11C5/14 ,  G11C5/147

Abstract: A semiconductor device having a first circuit block supplied with a first operating voltage, a second circuit block supplied with a second operating voltage, a voltage generating circuit for generating a third operating voltage in response to the first operating voltage, and a third circuit block supplied with the third operating voltage. Preferably, the third operating voltage is generated such that the first operating voltage is increased to a fourth operating voltage by a voltage-up converter, and then the fourth operating voltage is dropped to the third operating voltage by a voltage down-converter. Hence, a power supply operating internally stably in spite of use of a relatively fluctuating voltage can be provided even in the case where a power-supply voltage is dropped.

公开(公告)号：US20030107918A1

公开(公告)日：2003-06-12

申请号：US10269971

申请日：2002-10-15

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Hiyori Koyama ,  Kazuyoshi Oshima ,  Akihiko Hoshida ,  Kiichi Manita ,  Michitaro Kanamitsu ,  Shinji Udo ,  Kazue Kikuchi ,  Kazuaki Ujiie ,  Masahiro Sakai

IPC: G11C011/34

CPC classification number: G11C16/3436 ,  G11C16/04 ,  G11C29/44

Abstract: A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.

Abstract translation: 一种用于计数在诸如扇区的预定单元中执行的写入和擦除处理期间产生的失败次数的计数器电路和用于判断由计数器电路计数的值是否超过了数字的预设容许值的比较电路 提供失败。 因此，当计数器电路的计数值已经超过设置给寄存器的容许值时，即使从外部电路输入写入或擦除命令，也不执行写入处理或擦除处理。 因此，对于诸如闪存的电可编程和可擦除的非易失性半导体存储器件，可以缩短所需的测试时间。

公开(公告)号：US20030107403A1

公开(公告)日：2003-06-12

申请号：US10303841

申请日：2002-11-26

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

IPC: H03K019/0175

CPC classification number: H03K3/356113 ,  H01L2924/0002 ,  H03K3/356104 ,  H01L2924/00

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

公开(公告)号：US20130235668A1

公开(公告)日：2013-09-12

申请号：US13867055

申请日：2013-04-20

Applicant: RENESAS ELECTRONICS CORPORATION ,  HITACHI ULSI SYSTEMS CO., LTD.

Inventor： Toshihiro TANAKA ,  Yukiko UMEMOTO ,  Mitsuru HIRAKI ,  Yutaka SHINAGAWA ,  Masamichi FUJITO ,  Kazufumi SUZUKAWA ,  Hiroyuki TANIKAWA ,  Takashi YAMAKI ,  Yoshiaki KAMIGAKI ,  Shinichi MINAMI ,  Kozo KATAYAMA ,  Nozomu MATSUZAKI

IPC: G11C16/24 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

公开(公告)号：US20130229144A1

公开(公告)日：2013-09-05

申请号：US13757757

申请日：2013-02-02

Applicant: HITACHI ULSI SYSTEMS CO., LTD.

Inventor： Shogo Nagata ,  Yasuaki So ,  Takeshi Yamaguchi ,  Norihito Kawaguchi

IPC: H02J7/00

CPC classification number: H02J7/007 ,  G01R19/16542 ,  H01M10/4257 ,  H02J7/0004 ,  H02J7/0011 ,  H02J7/0029 ,  H02J7/0072 ,  H02J2007/0039 ,  Y02E60/12

Abstract: A secondary-battery monitoring device capable of realizing highly reliable overcurrent detection and a battery pack having it are provided. When an overcurrent flowing to a secondary battery is to be detected by utilizing a current detection voltage generated via on-resistance of a discharge-control switch and a charge-control switch, a voltage correction circuit that generates a correction voltage having a characteristic varied by positive slope or negative slope along with increase in a power supply voltage is provided, and the correction voltage is added to the detection voltage or a reference power supply voltage with the polarity that cancels out the slope of voltage variation caused in the detection voltage, and then the voltage is input to a comparator circuit. In this manner, variation in the overcurrent determination current is reduced.

Abstract translation: 提供能够实现高可靠性过电流检测的二次电池监视装置和具有该二次电池监视装置的电池组。 当通过利用通过放电控制开关和充电控制开关的导通电阻产生的电流检测电压来检测流过二次电池的过电流时，产生具有由 提供正斜率或负斜率以及电源电压的增加，并且将校正电压加到具有抵消检测电压引起的电压变化的斜率的极性的检测电压或参考电源电压，以及 然后将电压输入到比较器电路。 以这种方式，过电流确定电流的变化减小。

公开(公告)号：US20130187610A1

公开(公告)日：2013-07-25

申请号：US13749279

申请日：2013-01-24

Applicant: HITACHI ULSI SYSTEMS CO., LTD.

Inventor： Hirokatsu HAYASHI ,  Hiroyuki KATO ,  Hidetomo AOYAGI ,  Hitoshi ENDO

IPC: H02J7/00

CPC classification number: H02J7/00 ,  H02J7/0047 ,  H02J2007/005

Abstract: A charging/discharging monitoring device of a battery pack, includes: a plurality of monitoring integrated circuits; a plurality of wiring boards on which the plurality of monitoring integrated circuits are mounted, respectively; and a plurality of signal transmission paths for, via corresponded respective capacitors, connecting between the plurality of wiring boards. The charging/discharging monitoring device is configured with a two-wire transmission path for connecting between terminals of an upstream-side monitoring integrated circuit of daisy chain connection and a downstream-side monitoring integrated circuit thereof, and a wire length of a wiring part which connects between the respective capacitors and terminals of the corresponding monitoring integrated circuits on the wiring boards is a length in which resonance is not caused by the electromagnetic wave noises in an electromagnetic wave noise environment under which the wiring boards are arranged.

Abstract translation: 一种电池组的充电/放电监视装置，包括：多个监视集成电路; 分别安装有多个监视集成电路的多个布线板; 以及多个信号传输路径，用于经由相应的相应电容器在多个布线板之间进行连接。 充电/放电监视装置配置有用于连接菊花链连接的上游侧监视集成电路的端子与其下游侧监视集成电路的两线传输路径，以及布线部分的线长度 在布线板上的相应的监视集成电路的各个电容器和端子之间的连接是在布置有布线板的电磁波噪声环境中不会由电磁波噪声引起的谐振的长度。

公开(公告)号：US20040214428A1

公开(公告)日：2004-10-28

申请号：US10846571

申请日：2004-05-17

Applicant: Renesas Technology Corporation ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Ryouichi Furukawa ,  Kazuyuki Suko ,  Masayuki Hiranuma ,  Koichi Saitoh ,  Hirohiko Yamamoto ,  Tadanori Yoshida ,  Masayuki Ishizaka ,  Maki Shimoda

IPC: H01L021/00

CPC classification number: H01L21/76808 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76879 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/84 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.

Abstract translation: 导电层以如下方式形成在由绝缘膜制成的沟槽中。 首先，将非晶硅膜26A沉积在由氧化硅膜24制成的沟槽25中。然后通过旋涂在非晶硅膜26A上形成光致抗蚀剂膜30。 然后，将曝光光施加到光致抗蚀剂膜30的整个表面，从而将位于沟槽25外部的光致抗蚀剂膜30的那些部分曝光。位于沟槽25中的光致抗蚀剂膜30的其它部分是 没有光照，因为到达他们的光是不够的。 此外，光致抗蚀剂膜30被显影，从而除去位于沟槽25外部并暴露于光的膜30的那些部分。 此后，通过使用残留在沟槽25中的光致抗蚀剂膜30的未曝光部分作为掩模，通过干蚀刻去除位于沟槽25外部的非晶硅膜26A的那些部分。

公开(公告)号：US20040197959A1

公开(公告)日：2004-10-07

申请号：US10825678

申请日：2004-04-16

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Mikako Ujiie ,  Michiaki Sugiyama ,  Kazunari Suzuki ,  Masachika Masuda ,  Tamaki Wada

IPC: H01L021/48

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68331 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512

Abstract: A method of manufacturing a semiconductor device, comprises providing a wiring substrate having a main surface, an insulating film formed on the main surface, and electrodes formed on the main surface so as to be exposed from the insulating film. A semiconductor chip is adhesively fixed to the insulating film. Conductive wires connect the electrodes on the main surface of the wiring substrate and electrodes on the chip. A groove is formed between the chip and the electrodes on the substrate. A protruding portion of the adhesive stays within the groove and does not reach the electrodes on the substrate.

Abstract translation: 一种制造半导体器件的方法，包括提供具有主表面，形成在主表面上的绝缘膜和形成在主表面上的电极以从绝缘膜暴露的布线基板。 半导体芯片粘接固定在绝缘膜上。 导电线将布线基板的主表面上的电极和芯片上的电极连接起来。 在芯片和基板上的电极之间形成凹槽。 粘合剂的突出部分停留在凹槽内并且不会到达基底上的电极。

公开(公告)号：US20040186952A1

公开(公告)日：2004-09-23

申请号：US10765170

申请日：2004-01-28

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Mitsuo Hagiwara ,  Hiromasa Takahashi ,  Satoshi Yamato ,  Nobuo Shibasaki ,  Mitsuo Yotsutani ,  Tsutomu Ishii

IPC: G06F012/00

CPC classification number: G06F3/0614 ,  G06F3/0623 ,  G06F3/0632 ,  G06F3/0644 ,  G06F3/0658 ,  G06F3/0674 ,  G06F3/0676 ,  G06F3/0677 ,  G06F8/65 ,  G06F9/4401

Abstract: A microcomputer (5) which is an integrated circuit including an electrically erasable and programmable nonvolatile semiconductor memory (56) and a central processing unit (51) is used for control of a disk drive (2). The nonvolatile semiconductor memory holds an application program such as a recorded information reproducing control program in an application program area (561), and holds a reboot program used for updating the application program in a reboot program area (560). The central processing unit executes the reboot program to rewrite the application program in whole or part, in response to a rewrite command for the application program which is supplied from the outside. Accordingly, even after the microcomputer is mounted in the disk drive, it is possible to rewrite the whole or part of the application program in the nonvolatile semiconductor memory. At this time, since the reboot program area is not an area to be rewritten, even if an abnormality occurs during the rewriting of the nonvolatile semiconductor memory, it is possible to immediately transfer control to the operation of performing rewriting on the application program area, by again executing the reboot program.

Abstract translation: 作为包括电可擦除可编程非易失性半导体存储器（56）和中央处理单元（51）的集成电路的微型计算机（5）被用于控制盘驱动器（2）。 非易失性半导体存储器在应用程序区域（561）中保存诸如记录信息再现控制程序的应用程序，并且将重新启动程序保存在重新启动程序区域（560）中。 响应于从外部提供的应用程序的重写命令，中央处理单元执行重新启动程序以全部或部分重写应用程序。 因此，即使在将微型计算机安装在盘驱动器中之后，也可以将非法半导体存储器中的整个或部分应用程序重写。 此时，由于重新启动程序区域不是要重写的区域，即使在非易失性半导体存储器的重写期间发生异常，也可以立即将控制转移到对应用程序区域进行重写的操作， 通过再次执行重新启动程序。

公开(公告)号：US20040182992A1

公开(公告)日：2004-09-23

申请号：US10817042

申请日：2004-04-05

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd. ,  Hitachi Tohbu Semiconductor, Ltd.

Inventor： Yasutoshi Aibara ,  Hiroki Nakajima ,  Eiki Imaizumi ,  Tatsuji Matsuura

IPC: H01J040/14 ,  H03M007/30 ,  H03M003/00

CPC classification number: H04N5/357 ,  H04N5/335 ,  H04N5/3577 ,  H04N5/3698 ,  H04N5/378

Abstract: An AD-converted digital video data is encoded by a difference encoding method before it is outputted and such encoded digital video data is then outputted, after it is converted to gray code or to a predetermined code in which a fixed value is added. Problems solved include noise that is generated when the AD conversion circuit outputs video data and that migrates into a CCD side via a power supply line on a printed circuit board, and noise that appears on a display image by migration into an input terminal side from an output circuit side via the power supply line and a semiconductor substrate within an AD conversion LSI.

Abstract translation: AD转换的数字视频数据在输出之前由差分编码方法编码，然后在将其转换为灰度代码或添加固定值的预定代码之后输出这样的编码数字视频数据。 解决的问题包括当AD转换电路输出视频数据并经由印刷电路板上的电源线迁移到CCD侧时产生的噪声，以及通过从显示图像迁移到输入端侧而出现在显示图像上的噪声 输出电路侧经由AD转换LSI内的电源线和半导体基板。