公开(公告)号：WO1993017498A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001894

申请日：1993-02-23

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  ROSSEEL, Geert ,  HERNDON, William, H. ,  MATTHEWS, James, A.

IPC: H03K17/16

CPC classification number: H03K19/086 ,  H03K17/14 ,  H03K17/567 ,  H03K17/603 ,  H03K19/09448

Abstract: An improved BiCMOS logic circuit (70) utilizes an emitter-coupled pair of bipolar transistors (21, 22) for differentially comparing an input signal (Vin) with a logic reference level (VBIAS). Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors (26, 27) coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal (VREF2) providing a variable load resistance. The control signal is preferably provided by a feedback network (52, 53) which maintains a constant voltage swing across the network over temperature.

Abstract translation: 改进的BiCMOS逻辑电路（70）利用发射极耦合的双极晶体管（21,22）来差分地比较输入信号（Vin）与逻辑参考电平（VBIAS）。 每个双极晶体管由并联耦合的p沟道金属氧化物半导体（PMOS）晶体管（26,27）的网络进行电阻负载。 晶体管的并联组合中的至少一个具有耦合到提供可变负载电阻的控制信号（VREF2）的栅极。 控制信号优选地由反馈网络（52,53）提供，反馈网络（52,53）通过温度在网络上保持恒定的电压摆幅。

公开(公告)号：WO1992017745A1

公开(公告)日：1992-10-15

申请号：PCT/US1992002622

申请日：1992-03-31

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: F28F07/02

CPC classification number: F28F3/12 ,  F28D2021/0029 ,  F28F2260/02 ,  H01L23/473 ,  H01L2924/0002 ,  Y10T29/49366 ,  Y10T29/49368 ,  H01L2924/00

Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates (10), laminated together to form a block (18). Each plate has a pair of holes (14, 15) cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

公开(公告)号：WO1991011019A1

公开(公告)日：1991-07-25

申请号：PCT/US1991000211

申请日：1991-01-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: H01L21/225

CPC classification number: H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136 ,  H01L2924/00

Abstract: A method for forming a BICMOS integrated circuit having MOS field effect transistors and bipolar junction transistors is disclosed. The process comprises first defining separate active areas, forming a gate dielectric layer and a first layer of polysilicon. This polysilicon is then selectively etched to form a plurality of equally-spaced first polysilicon members comprising the gates (33, 34) of the MOS transistors and the extrinsic base contacts (35) of the NPN transistors. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members (65, 66, 67, 68, 69). Impurities are diffused from the polysilicon members to form source/drain regions (73, 74, 75, 76) of the MOS transistors and the extrinsic base (81) and emitter (77) regions of the NPN transistors. The final processing steps include providing the interconnection of the MOS and NPN transistors.

公开(公告)号：WO2016003820A9

公开(公告)日：2016-01-07

申请号：PCT/US2015/038078

申请日：2015-06-26

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC: G06F9/30

Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

公开(公告)号：WO1997045772A1

公开(公告)日：1997-12-04

申请号：PCT/US1997008418

申请日：1997-05-27

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  CHEN, J., Fung

IPC: G03F09/00

CPC classification number: G03F1/36 ,  G03F7/70433

Abstract: There is disclosed a photolithography mask and method of making the same that utilizes serifs to increase to correspondence between an actual circuit design and the final circuit pattern on a semiconductor wafer. The mask uses a plurality of serifs having a size determined by a resolution limit of the optical exposure tool used during the fabrication process. The serifs are positioned on the corner regions of the mask such that a portion of surface area for each of the serifs overlaps the corner regions of the mask. The size of the serifs is about one-third the resolution limit of said optical exposure tool. About 33 to about 40 percent of the total surface area of the serifs overlap the corner regions of the mask.

Abstract translation: 公开了一种光刻掩模及其制造方法，其利用衬底来增加实际电路设计和半导体晶片上的最终电路图案之间的对应关系。 掩模使用多个衬线，其具有由在制造过程中使用的光学曝光工具的分辨率极限确定的尺寸。 衬线位于掩模的拐角区域上，使得每个衬线的表面积的一部分与掩模的拐角区域重叠。 衬线的尺寸约为所述光学曝光工具的分辨率极限的三分之一。 衬线的总表面积的约33％至约40％与掩模的拐角区域重叠。

公开(公告)号：WO1997014084A2

公开(公告)日：1997-04-17

申请号：PCT/US1996016297

申请日：1996-10-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  HANSEN, Craig, C.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F00/00

CPC classification number: G06F12/0284 ,  G06F12/1045 ,  G06F12/1491

Abstract: A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Local-to-global virtual translation is performed by either mapping local virtual addresses to a single global virtual address space or to multiple global virtual address spaces. The local-to-global virtual translator includes a cell which corresponds to each local address space for performing the translations. Separate cache and tag structures are employed for handling data and instruction memory accesses. The cache can be configured into a buffer portion or a cache portion for faster cache accesses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit, cache miss, or buffer access occurs during a given data or instruction access. Memory area privilege protection is also achieved by employing a gateway instruction which generates an address to access a gateway storage area.

Abstract translation: 一种包括本地到全局虚拟地址转换器的虚拟存储器系统，用于将具有相关联的任务特定地址空间的本地虚拟地址转换成对应于与多个任务相关联的地址空间的全局虚拟地址，以及全局虚拟到物理地址转换器， 将全局虚拟地址转换为物理地址。 通过将本地虚拟地址映射到单个全局虚拟地址空间或多个全局虚拟地址空间来执行本地到全局虚拟转换。 本地到全球的虚拟翻译器包括对应于用于执行翻译的每个本地地址空间的单元。 采用独立的缓存和标签结构来处理数据和指令存储器访问。 高速缓存可以被配置成缓冲部分或高速缓存部分，以便更快的高速缓存访​​问。 保护信息由本地虚拟到全局虚拟地址转换器，全球虚拟到物理地址转换器，高速缓存标签存储器或保护信息缓冲器中的每一个提供，取决于缓存命中，高速缓存未命中或缓冲器 在给定的数据或指令访问期间进行访问。 存储区域特权保护也可以通过采用生成访问网关存储区域的地址的网关指令来实现。

公开(公告)号：WO1996008871A1

公开(公告)日：1996-03-21

申请号：PCT/US1995011718

申请日：1995-09-14

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CAMPBELL, John, G. ,  WONG, Ban, Pak

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H03K19/0175

CPC classification number: H03K19/0136 ,  H03K19/00353 ,  H03K19/017581

Abstract: An output buffer that controls the slew rate of its output signal is disclosed. The buffer includes a pull-up and a pull-down bipolar transistor (Q1, Q2) coupled at a common output node in series between VDD and VSS. The buffer also includes a first set of parallel MOS devices (N5-N8) coupled between the common output node and the base of the pull-down bipolar transistor (Q2). A second set of parallel MOS devices (P1-P4) are coupled between the base of the pull-up output stage bipolar transistor (Q1) and VDD. The gates of each set of MOS devices are coupled to a digital select signal. The amount of current driving the base of each of the pull-up and pull-down transistors (when they are enabled) is determined by the number of MOS devices enabled by the digital select signal. Thus, the buffer of the present invention is able to adjust the slew rate of its output signal to accommodate different loads coupled to the common output node.

Abstract translation: 公开了一种控制其输出信号的转换速率的输出缓冲器。 该缓冲器包括一个上拉电阻和一个下拉双极晶体管（Q1，Q2），耦合在VDD和VSS之间串联的公共输出节点。 缓冲器还包括耦合在公共输出节点和下拉双极晶体管（Q2）的基极之间的第一组并联MOS器件（N5-N8）。 第二组并联MOS器件（P1-P4）耦合在上拉输出级双极晶体管（Q1）的基极和VDD之间。 每组MOS器件的栅极耦合到数字选择信号。 每个上拉和下拉晶体管（当它们被使能时）驱动基极的电流量由数字选择信号使能的MOS器件的数量决定。 因此，本发明的缓冲器能够调节其输出信号的转换速率以适应耦合到公共输出节点的不同负载。

公开(公告)号：WO1995020223A1

公开(公告)日：1995-07-27

申请号：PCT/US1995000816

申请日：1995-01-20

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  WONG, Ban, Pak ,  CAMPBELL, John, G.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G11C11/41

CPC classification number: G11C11/41

Abstract: A current mode access BiCMOS memory cell is disclosed. The memory cell includes a CMOS storage cell for storing first and second CMOS voltage potentials, VDD and VSS, corresponding to first and second logic levels. The storage cell comprises two CMOS inverters coupled between VDD and VSS. The storage cell is coupled to a conversion circuit. The conversion circuit is coupled between third and fourth ECL working potentials. It functions to convert the first and second CMOS voltage potentials into the third and fourth working potentials. The third and fourth voltage potentials are coupled to the bases of two bipolar signal converters. The emitters of the bipolar signal converters are coupled to a selectable current source and the collectors of the bipolar signal converters are coupled to complementary bit lines. The selectable current source is responsive to a read word signal. A differential current signal representing the data stored in the memory cell is established in the complementary bit lines when the current source is selected and current is allowed to flow through one of the bipolar signal converters. The third and fourth ECL voltage potentials are chosen such that they ensure that the bipolar signal converters are not driven into saturation. In this way, read times are optimized. In addition, read times are reduced since peak-to-peak voltages of the current mode differential signal established across the complementary bit lines are reduced.

Abstract translation: 公开了一种电流模式存取BiCMOS存储单元。 存储单元包括用于存储对应于第一和第二逻辑电平的第一和第二CMOS电压电位VDD和VSS的CMOS存储单元。 存储单元包括耦合在VDD和VSS之间的两个CMOS反相器。 存储单元耦合到转换电路。 转换电路耦合在第三和第四ECL工作电位之间。 它用于将第一和第二CMOS电压电位转换为第三和第四工作电位。 第三和第四电压电位耦合到两个双极性信号转换器的基极。 双极性信号转换器的发射极耦合到可选择的电流源，并且双极性信号转换器的集电极耦合到互补位线。 可选择的电流源响应于读取字信号。 当选择电流源并且允许电流流过双极型信号转换器之一时，表示存储在存储单元中的数据的差分电流信号被建立在互补位线中。 选择第三和第四ECL电压电位，使得它们确保双极性信号转换器不被驱动到饱和。 以这种方式，优化了阅读时间。 此外，由于在互补位线上建立的电流模式差分信号的峰 - 峰电压减小，所以读取时间减少。

公开(公告)号：WO1994029870A1

公开(公告)日：1994-12-22

申请号：PCT/US1994004615

申请日：1994-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  ROBINSON, Timothy, B. ,  CAMPBELL, John, G. ,  HANSEN, Craig, C.

IPC: G11C07/00

CPC classification number: G11C7/1039 ,  G11C5/025

Abstract: A large burst mode memory (10) accessing system (15) includes N discrete sub-memories (11, 12) and three main I/O ports (17, 18, 19). Data is stored in the sub-memories so that the sub-memories (11, 12) are accessed depending on their proximity to the main I/O ports (17, 18, 19). Three parallel pipelines (1, 2, 3) provide a data path to/from the main I/O ports (17, 18, 19) and the sub-memories (11, 12). The first pipeline (1) functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline (2) functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline (3) propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.

Abstract translation: 大型突发模式存储器（10）访问系统（15）包括N个离散子存储器（11,12）和三个主要I / O端口（17,18,19）。 数据被存储在子存储器中，使得子存储器（11,12）根据其与主I / O端口（17,18,19）的接近度被访问。 三条并行的管道（1,2,3）为主I / O端口（17,18,19）和子存储器（11,12）提供数据路径。 第一管线（1）用于将地址/控制信号耦合到存储器，使得相邻子存储器以半周期间隔被访问。 第二管线（2）用于将访问数据从子存储器传播到主I / O端口，使得每个连续时钟周期从主输出端口输出数据。 第三流水线（3）将写数据传播到存储器，使得在连续时钟周期的第三流水线的输入处呈现的数据被写入连续的子存储器。 冗余电路保留数据完整性，无需存储器访问中断。

公开(公告)号：WO1993017461A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001203

申请日：1993-02-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: H01L29/72

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L29/0826 ,  Y10S257/927

Abstract: A bipolar junction transistor (BJT) which exhibits a suppressed Kirk Effect comprises a lightly-doped n-type collector region (11) formed above a more heavily-doped n+ layer (12). Directly above the collector is a p-type base which has an extrinsic region (17) disposed laterally about an intrinsic region (18). An n+ emitter (20) is positioned directly above the intrinsic base region. The BJT also includes a localized n+ region (15) disposed directly beneath the intrinsic base region which significantly increases the current handling capabilities of the transistor.

Abstract translation: 显示抑制Kirk效应的双极结型晶体管（BJT）包括形成在更重掺杂的n +层（12）上方的轻掺杂的n型集电极区域（11）。 集电极的正上方是p型基体，其具有围绕本征区域横向设置的非本征区域（17）。 n +发射极（20）位于本征基极区的正上方。 BJT还包括直接位于本征基极区下方的局部n +区（15），这显着增加了晶体管的电流处理能力。