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51.发明专利
公开(公告)号：JP2004297069A
公开(公告)日：2004-10-21
申请号：JP2004091404
申请日：2004-03-26
Inventor： HARRY MICHAEL SIEGEL , ANTHONY M CHU
IPC: H01L23/367 , H01L23/433 , H01L23/473
CPC classification number: H01L23/473 , H01L23/3675 , H01L23/4334 , H01L2924/0002 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a technology for removing heat efficiently from a type of an integrated circuit that has an exposed portion of the integrated circuit die. SOLUTION: The invention comprises a lid that is capable of being placed in contact with and attached to the integrated circuit that has the exposed surface of the integrated circuit die. The lid has portions that form a cavity between a surface of the lid and the exposed surface of the integrated circuit die when the lid is placed in contact with the integrated circuit. The lid also has portions that form a first fluid conduit for transporting a fluid into the cavity and a second fluid conduit for transporting the fluid out of the cavity. Heat from the integrated circuit die is absorbed by the fluid by direct convection and removed from the integrated circuit when the fluid is removed from the cavity. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供从具有集成电路管芯的暴露部分的集成电路的类型中有效地去除热的技术。 解决方案：本发明包括能够被放置成与具有集成电路管芯的暴露表面的集成电路接触并附接的盖。 当盖与集成电路接触时，盖具有在盖的表面和集成电路裸片的暴露表面之间形成空腔的部分。 盖子还具有形成用于将流体输送到空腔中的第一流体导管和用于将流体输送出空腔的第二流体导管的部分。 来自集成电路管芯的热量通过直接对流被流体吸收，并且当流体从空腔中移出时从集成电路移除。 版权所有（C）2005，JPO＆NCIPI
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52.发明专利
公开(公告)号：JP2004280817A
公开(公告)日：2004-10-07
申请号：JP2004069672
申请日：2004-03-11
Inventor： FRUHAUF SERGE , TAMAGNO DAVID , TOURNEMILLE JEROME
CPC classification number: G06K19/07733 , G06K7/10297 , G06K19/07 , G06Q20/105
Abstract: PROBLEM TO BE SOLVED: To provide a technique of performing the debug and software development of a dual mode smart card. SOLUTION: An integrated circuit and method used together with a smart card is operable in both ISO mode based on International Standardization Organization 7816 (ISO 7816) protocol and non-ISO mode based on non-ISO protocol. A dual mode integrated circuit includes a microprocessor and a switching block. The circuit includes an ISO port operable for making communication in the ISO mode when an external interface is connected to the switching block and the ISO mode is detected, and a non-ISO port operable to make communication in the non-ISO mode when the non-ISO mode is detected. The ISO port is form-specified to enable the debug and/or software development via a serial interface in the non-ISO mode. The non-ISO port is form-specified to enable the debug and/or software development via the non-ISO port in the ISO mode. COPYRIGHT: (C)2005,JPO&NCIPI
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公开(公告)号：JP2008289117A
公开(公告)日：2008-11-27
申请号：JP2008002131
申请日：2008-01-09
Inventor： CHU LIWEN , HU WENDONG , VLANTIS GEORGE A
CPC classification number: H04B1/715 , H04B1/7143 , H04B2001/7154 , H04W84/14
Abstract: PROBLEM TO BE SOLVED: To provide systems and methods for enhanced DFH (dynamic frequency hopping) among a plurality of WRAN (wireless regional area network) cells.
SOLUTION: A dynamic frequency hopping community (DFH community) is formed from a plurality of wireless regional area network (WRAN) cells, wherein each of the plurality of WRAN cells within the DFH community is a one-hop neighbor of the leader cell. The leader cell sets and distributes a hopping pattern for use among the WRAN cells, on the basis of, in part, the number of usable channels and whether a WRAN cell is shared by two groups in the DFH Community.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：提供多个WRAN（无线区域网络）小区之间用于增强的DFH（动态跳频）的系统和方法。 解决方案：从多个无线区域网络（WRAN）小区形成动态跳频社区（DFH community），其中DFH社区内的多个WRAN小区中的每一个都是领导者的一跳邻居 细胞。 领导单元基于部分可用信道的数量以及DFH群组中的两个群组共享一个WRAN小区来设置和分配在WRAN小区之间使用的跳频模式。 版权所有（C）2009，JPO＆INPIT
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54.发明专利
公开(公告)号：JP2006180509A
公开(公告)日：2006-07-06
申请号：JP2005368483
申请日：2005-12-21
Inventor： DANG PHILIP P
IPC: H04N19/50
CPC classification number: H04N19/523 , H04N19/43 , H04N19/436
Abstract: PROBLEM TO BE SOLVED: To provide a method and system for fast implementation of subpixel interpolation. SOLUTION: A subpixel interpolator includes an input memory capable of storing video information formed from full pixels. The subpixel interpolator also includes at least one interpolation unit capable of performing subpixel interpolation to generate half-pixels and quarter-pixels in parallel. Multiple half-pixels and multiple quarter-pixels are generated concurrently during the subpixel interpolation. In addition, the subpixel interpolator includes an output memory capable of storing at least some of the full pixels, half-pixels, and quarter-pixels. In some embodiments, at least one interpolation unit includes a horizontal half-pixel interpolation unit, two vertical half-pixel interpolation units, and a quarter-pixel interpolation unit, all of which may operate in parallel. In particular embodiments, the interpolation units are formed from adders and shifters and do not include any multipliers. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种快速实现子像素插值的方法和系统。 解决方案：子像素插值器包括能够存储从全像素形成的视频信息的输入存储器。 子像素内插器还包括能够执行子像素内插以平行生成半像素和四分之一像素的至少一个内插单元。 在子像素插值期间同时产生多个半像素和多个四分之一像素。 此外，子像素内插器包括能够存储全像素，半像素和四分之一像素中的至少一些的输出存储器。 在一些实施例中，至少一个内插单元包括水平半像素内插单元，两个垂直半像素内插单元和四分之一像素内插单元，所有这些都可以并行操作。 在特定实施例中，插值单元由加法器和移位器形成，并且不包括任何乘法器。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006019006A
公开(公告)日：2006-01-19
申请号：JP2005189888
申请日：2005-06-29
Inventor： FREY CHRISTOPHE
IPC: G11C11/15 , H01L21/8246 , H01L27/105
CPC classification number: G11C11/16 , G11C11/5607
Abstract: PROBLEM TO BE SOLVED: To provide a magnetic random access memory element which can store multi-bits.
SOLUTION: The magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. These magnetic tunnel junctions are connected to each other in a series resistive circuit. The connected first and second magnetic tunnel junctions are connected to a bit line through an access transistor. A write bit line and a write data line are associated with each of the first and second magnetic tunnel junctions. By application of appropriate currents to these lines , the magnetic vector orientation with each of the first and second magnetic tunnel junctions can be controlled so as to store within the element in any one of at least three logic states.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：提供可以存储多位的磁性随机存取存储元件。 解决方案：磁性随机存取存储元件由第一磁性隧道结和第二磁性隧道结构成。 这些磁性隧道结在串联电阻电路中相互连接。 连接的第一和第二磁性隧道结通过存取晶体管连接到位线。 写入位线和写入数据线与第一和第二磁性隧道结中的每一个相关联。 通过向这些线路施加适当的电流，可以控制与第一和第二磁性隧道结中的每一个的磁矢量取向，以便以至少三个逻辑状态中的任何一个存储在元件内。 版权所有（C）2006，JPO＆NCIPI
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Patent Agency Ranking56.发明专利Apparatus and method using hashing for efficiently implementing ip lookup solution in hardware 审中-公开使用HASHING有效地实现硬件中的IP查找解决方案的装置和方法
公开(公告)号：JP2005198285A
公开(公告)日：2005-07-21
申请号：JP2004374336
申请日：2004-12-24
Inventor： RAJGOPAL SURESH , HUANG LUN-BIN , RICHARDSON NICHOLAS
CPC classification number: H04L45/00 , H04L45/745 , H04L45/7453 , H04L45/7457 , H04L49/25 , H04L49/55
Abstract: PROBLEM TO BE SOLVED: To provide an advanced IP address lookup technology. SOLUTION: Internet Protocol address prefixes are hashed into hash tables allocated memory blocks on demand after collisions occur for both a first hash and a single rehash. The number of memory blocks allocated to each hash table is limited, with additional prefixes, handled by an overflow content addressable memory. Each hash table contains only prefixes of a particular length, different hash tables contain prefixes of different lengths. Only subset of possible prefix lengths are accommodated by the hash tables, a remainder of prefixes is handled by the content addressable memory or a similar alternate address lookup facility. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供高级IP地址查找技术。 解决方案：互联网协议地址前缀在哈希表中被散列成分配的内存块，在第一个哈希和单个重新发生冲突之后也可以。 分配给每个哈希表的存储器块的数量受限于额外的前缀，由溢出内容可寻址存储器处理。 每个散列表仅包含特定长度的前缀，不同的散列表包含不同长度的前缀。 只有哈希表容纳了可能的前缀长度的子集，剩余的前缀由内容可寻址存储器或类似的备用地址查找工具来处理。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2005182989A
公开(公告)日：2005-07-07
申请号：JP2004365219
申请日：2004-12-17
Inventor： WORLEY JAMES L
CPC classification number: H03M13/095
Abstract: PROBLEM TO BE SOLVED: To provide technique for performing error correction and error detection on a wide data word in a memory system and other systems including a memory.
SOLUTION: A parity generation circuit includes a plurality of bit generation circuits. Each of the bit generation circuits operates to receive each data bit and each hard latch signal, and generate a parity signal indicating the parity of the corresponding data bit when the hard latch signal is inactive. Each of the bit generation circuits drives the parity signal to a setting value when the hard latch signal is active. An output circuit is coupled with a bit generation circuit to receive the parity signal, and operates to generate an output parity signal in response to the parity signal from the bit generation circuit.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供对存储器系统和包括存储器的其他系统中的宽数据字执行纠错和错误检测的技术。 解决方案：奇偶产生电路包括多个位产生电路。 每个位产生电路操作以接收每个数据位和每个硬锁存信号，并且当硬锁存信号不活动时，产生指示相应数据位的奇偶性的奇偶校验信号。 当硬锁存信号有效时，位产生电路中的每一个将奇偶校验信号驱动到设定值。 输出电路与位生成电路耦合以接收奇偶信号，并且响应于来自位产生电路的奇偶校验信号而操作以产生输出奇偶校验信号。 版权所有（C）2005，JPO＆NCIPI
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58.发明专利Integrated and released beam layer structure manufactured in trench and its manufacturing method 有权一体化和释放的梁结构在TRENCH中制造及其制造方法
公开(公告)号：JP2005169616A
公开(公告)日：2005-06-30
申请号：JP2004340417
申请日：2004-11-25
Inventor： BLANCHARD RICHARD A , MCALEXANDER JOSEPH C
IPC: G01P15/135 , B81B3/00 , B81C1/00 , G01K5/62 , G01P15/18
CPC classification number: B81C1/00626 , B81B2201/0235 , B81B2203/0118 , B81B2203/033 , B81C2201/0109 , B81C2201/014
Abstract: PROBLEM TO BE SOLVED: To provide an integrated and released beam layer structure manufactured in a trench and its manufacturing method.
SOLUTION: The beam layer structure has a semiconductor substrate 20, the trench 18, a first electrical conducting layer 24, and the beam 28. The trench is extended inside the semiconductor substrate and has a wall. The first electrical conducting layer is positioned on the wall of the trench in the selected position. The beam is positioned on the trench, and the first part of it is connected to the semiconductor substrate, and a second part of it is movable. The second part of the beam is separated from the wall of the trench by the selected distance. Therefore, the second part of the beam is freely movable inside the plane vertical or parallel to the surface of the substrate, and can be deflected, that is, deformed relative to the trench so as to electrically contact in response to a predetermined acceleration force applied to the beam structure or the change of a predetermined temperature.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供在沟槽中制造的集成和释放的束层结构及其制造方法。 解决方案：光束层结构具有半导体衬底20，沟槽18，第一导电层24和光束28.沟槽在半导体衬底的内部延伸并具有壁。 第一导电层位于选择位置的沟槽壁上。 光束定位在沟槽上，其第一部分连接到半导体衬底，其第二部分是可移动的。 梁的第二部分与沟槽的壁分开一定距离。 因此，梁的第二部分可以在垂直或平行于基板的表面的平面内自由移动，并且可以被偏转，即相对于沟槽变形，以便响应于施加的预定加速力而电接触 到梁结构或预定温度的变化。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2005135574A
公开(公告)日：2005-05-26
申请号：JP2004312044
申请日：2004-10-27
Inventor： MA HERMAN
IPC: G11C13/00 , G11C16/02 , G11C16/26 , H01L27/105 , H01L27/10
CPC classification number: G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/79
Abstract: PROBLEM TO BE SOLVED: To provide an improved semiconductor memory device in which comparatively high-speed phase change material is used. SOLUTION: The device is a circuit and a method for the memory device for a phase change memory, and the like. A memory 1 having a plurality of columns of a memory cells 2 is especially provided, and each column of the memory cells is connected to a bit line 4 or a data line. Each of the memory cells includes a programmable resistance element connected in series to a selection transistor. Each of the bit lines is connected to a separate reference cell and a separate transistor. The transistor is connected between the corresponding bit line and reference voltage such as grounding, and the like. During the period of the memory read operation, the transistor, the reference cell and the addressed memory cell form a differential amplifier circuit. Output from the differential amplifier circuit is connected to a data output terminal for the phase change memory. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 解决的问题：提供一种使用比较高速的相变材料的改进的半导体存储器件。 解决方案：该装置是用于相变存储器的存储装置的电路和方法等。 特别提供具有存储单元2的多列的存储器1，并且每列存储单元连接到位线4或数据线。 每个存储单元包括与选择晶体管串联连接的可编程电阻元件。 每个位线连接到单独的参考单元和单独的晶体管。 晶体管连接在相应的位线和参考电压如接地等之间。 在存储器读取操作期间，晶体管，参考单元和寻址的存储单元形成差分放大器电路。 差分放大电路的输出与相变存储器的数据输出端子连接。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2005065491A
公开(公告)日：2005-03-10
申请号：JP2004231534
申请日：2004-08-06
Inventor： SHAO JIANWEN , HOPKINS THOMAS L
Abstract: PROBLEM TO BE SOLVED: To provide a technique to determine the direction of rotation of a sensorless motor operating in the state of freewheel, by comparing signals induced in a motor winding. SOLUTION: A device and method for determining the freewheel rotation of an electric motor is provided comprises a step to measure first and second signals from first and second windings of an unenergized motor, respectively, and a step to determine whether or not an energized motor is rotating from the first and second signals. The method can also determine the direction of rotation from the first and second signals when the unenergized motor is rotating. Further the method can measure a third signal from a third winding of the unenergized motor, and when determining whether or not the motor is rotating the method can determine that the motor is not rotating if the first, second and third signals are equal. Each of the first and second signals can have a back-voltage. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：通过比较在电动机绕组中感应的信号，提供一种确定在自由轮状态下工作的无传感器电动机的旋转方向的技术。 解决方案：提供一种用于确定电动机的自由轮旋转的装置和方法，包括分别测量未通电电动机的第一和第二绕组的第一和第二信号的步骤，以及确定是否 通电电动机从第一和第二信号旋转。 该方法还可以在非电动马达旋转时从第一和第二信号确定旋转方向。 此外，该方法可以测量来自未通电电动机的第三绕组的第三信号，并且当确定电动机是否旋转时，如果第一，第二和第三信号相等，则该方法可以确定电动机不旋转。 第一和第二信号中的每一个可以具有反向电压。 版权所有（C）2005，JPO＆NCIPI
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