公开(公告)号：US20040119618A1

公开(公告)日：2004-06-24

申请号：US10632564

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.I.

Inventor： Philip Mattos ,  Marco Losi

IPC: H03M009/00

CPC classification number: H03H17/0664 ,  G01S19/30

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a separate acquisition engine is used which includes a sample reducer for combining samples of a received signal for correlation with a locally generated version of a GPS code. A serial to parallel converter converts the reduced samples to parallel words which are correlated in parallel with locally generated words of the GPS code.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，使用单独的采集引擎，其包括用于组合接收信号的采样以与本地生成的GPS码版本进行相关的采样减速器。 串行到并行转换器将缩减的样本转换成与GPS码的本地生成的字并行相关的并行字。

公开(公告)号：US20040119528A1

公开(公告)日：2004-06-24

申请号：US10620834

申请日：2003-07-15

Applicant: STMicroelectronics Limited

Inventor： Tahir Rashid

IPC: G05F003/02

CPC classification number: G05F3/225 ,  G05F3/30

Abstract: The described embodiments of the invention relate to a voltage reference generator which can be produced using new process technologies and which is still compatible with older designs/products. This is achieved by the introduction of circuitry to generate an offset voltage independently of the main reference voltage generation circuitry.

Abstract translation: 所描述的本发明的实施例涉及一种可以使用新的工艺技术制造的并且与旧的设计/产品兼容的电压参考发生器。 这通过引入电路来实现，以产生独立于主参考电压产生电路的偏移电压。

公开(公告)号：US20030185067A1

公开(公告)日：2003-10-02

申请号：US10354908

申请日：2003-01-30

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: G11C007/00

CPC classification number: G06F13/28

Abstract: A semiconductor integrated circuit for use in direct memory access (DMA) has two sources which communicate with a bus through a bus interface. A DMA access signal generator is coupled to the bus interface and asserts a DMA access output signal at a DMA access signal pin whenever either of the sources requires a DMA access. The need for separate DMA access signal pins for each of the two sources is thereby avoided. With targets on two separate integrated circuits, a single DMA access pin can be used for the two targets, while chip select signals at chip select pins on the source integrated circuit indicate which of the two targets is intended for the DMA access.

Abstract translation: 用于直接存储器访问（DMA）的半导体集成电路具有通过总线接口与总线通信的两个源。 DMA访问信号发生器耦合到总线接口，并且每当任何一个源需要DMA访问时，在DMA访问信号引脚处断言DMA访问输出信号。 因此避免了对于两个源中的每一个的单独的DMA访问信号引脚的需要。 通过两个独立的集成电路上的目标，两个目标可以使用单个DMA访问引脚，而源集成电路芯片选择引脚上的芯片选择信号指示两个目标中的哪一个用于DMA访问。

公开(公告)号：US20030177483A1

公开(公告)日：2003-09-18

申请号：US10099455

申请日：2002-03-14

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Peter Hedinger

IPC: G06F009/44

CPC classification number: G06F12/126 ,  G06F8/54

Abstract: A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.

Abstract translation: 一种链接多个对象文件以生成可执行程序的方法，所述方法包括在执行程序时在目标文件中识别要被锁定到高速缓存中的至少一个例程，将所述例程定位在一组存储器地址 到一组缓存位置，并将映射到同一组高速缓存位置的其他存储器地址集合引入可执行程序间隙。

公开(公告)号：US20030137861A1

公开(公告)日：2003-07-24

申请号：US10229337

申请日：2002-08-26

Applicant: STMicroelectronics Limited

Inventor： William Thies ,  Nicolas Froidevaux

IPC: G11C005/06

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/06153

Abstract: A method of producing a semiconductor circuit is disclosed with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.

Abstract translation: 公开了一种制造半导体电路的方法，与常规电路布局相比，具有节省的面积。 IO单元被布置成宽度乘以因子，但具有相应减小的高度。 与常规安排相比，ESD保护电路以降低的速度被包括在内。 通过占用由ESD电路与IO电路一起使用的半导体区域来实现节省空间。 ESD保护保持在不同的位置。

公开(公告)号：US20020154636A1

公开(公告)日：2002-10-24

申请号：US10107602

申请日：2002-03-27

Applicant: STMicroelectronics Limited

Inventor： Tom Thomas

IPC: H04L012/28

CPC classification number: H04L63/0428 ,  H04L45/742

Abstract: A method of locating packet identifiers held in respective memory locations in a memory, the method comprising receiving a plurality of packets, each packet including a packet identifier, searching said memory locations in a sequence to compare an incoming packet identifier with packet identifiers stored in the memory until a match is found, incrementing one of a set of counters associated respectively with the memory locations, said incremented counter being the one associated with the memory location where the match packet identifier is held, and reading values of each of the counters and using said values to determine the sequence in which the memory locations are searched for subsequent incoming packet identifiers.

Abstract translation: 一种定位保存在存储器中的相应存储器位置中的分组标识符的方法，所述方法包括接收多个分组，每个分组包括分组标识符，在序列中搜索所述存储器位置，以将输入分组标识符与存储在 存储器，直到找到匹配，递增与存储器位置相关联的一组计数器中的一个计数器，所述递增计数器是与保持匹配分组标识符的存储器位置相关联的计数器，以及每个计数器的读取值并使用 所述值用于确定搜索存储器位置以用于后续传入分组标识符的顺序。

公开(公告)号：EP1367484B1

公开(公告)日：2013-07-24

申请号：EP02253869.8

申请日：2002-05-31

Applicant: STMicroelectronics Limited

Inventor： Hussain, Zahid

IPC: G06F9/38

CPC classification number: G06F9/3853

公开(公告)号：EP1898224B1

公开(公告)日：2013-03-13

申请号：EP07253248.4

申请日：2007-08-17

Applicant: STMicroelectronics Limited (Hong Kong)

Inventor： Gorbachov, Oleksandr, c/o STMicroelectronics

IPC: H01P5/18 ,  G01R27/06 ,  H03H7/48

CPC classification number: G01R27/06 ,  H01P5/185 ,  H03H7/46 ,  H03H7/48

公开(公告)号：EP1898224A3

公开(公告)日：2012-01-11

申请号：EP07253248.4

申请日：2007-08-17

Applicant: STMicroelectronics Limited (Hong Kong)

Inventor： Gorbachov, Oleksandr, c/o STMicroelectronics

IPC: H01P5/18 ,  G01R27/06 ,  H03H7/48

CPC classification number: G01R27/06 ,  H01P5/185 ,  H03H7/46 ,  H03H7/48

Abstract: Very small size true directional couplers (100) have a coupling coefficient that is independent on load VSWR. The coupler (100) uses coupled inductors (114,116,118) with a compensation circuit including a resistor (112) and a capacitor (110), or just a capacitor (110). Wideband operation is suitable for many portable applications such as power detection (306) and control for GSM (302), DCS-PCS (310), CDMA/WCDMA, Bluetooth, and WLAN systems.

公开(公告)号：EP2309759A1

公开(公告)日：2011-04-13

申请号：EP10183232.7

申请日：2002-03-18

Applicant: STMicroelectronics Limited

Inventor： Bolton, Martin

IPC: H04N7/50 ,  H04N7/26

CPC classification number: H04N19/42 ,  H04N19/126 ,  H04N19/13 ,  H04N19/137 ,  H04N19/15 ,  H04N19/172 ,  H04N19/176 ,  H04N19/61 ,  H04N19/91

Abstract: Decoding circuitry for decoding a bitstream, the circuitry including: a processor, the processor being configured to run software for: inverse quantising quantised macroblocks to generate inverse quantised macroblocks; a streaming data connection for streaming the inverse quantised macroblocks from the processor; inverse discrete cosine transform IDCT circuitry for accepting the streamed inverse quantised macroblocks and IDCT transforming them to generate reconstructed prediction error macroblocks; and an addition circuit for adding each reconstructed prediction error macroblock and its corresponding predictor macroblock, thereby to generate a respective reconstructed macroblock.

Abstract translation: 用于解码比特流的解码电路，所述电路包括：处理器，所述处理器被配置为运行软件，用于：对量化的宏块进行逆量化以产生逆量化宏块; 流式数据连接，用于从处理器流式传输逆向量化的宏块; 逆离散余弦变换IDCT电路，用于接受流式逆量化宏块和IDCT变换它们以产生重建的预测误差宏块; 以及加法电路，用于添加每个重建的预测误差宏块及其对应的预测器宏块，从而生成相应的重构宏块。