公开(公告)号：US20190294572A1

公开(公告)日：2019-09-26

申请号：US16360229

申请日：2019-03-21

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GmbH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20190007201A1

公开(公告)日：2019-01-03

申请号：US16022033

申请日：2018-06-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Roberto Colombo ,  Guido Marco Bertoni ,  William Orlando ,  Roberta Vittimani

IPC: H04L9/08 ,  H04L9/14 ,  G06F13/36

Abstract: A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.

公开(公告)号：US20180357012A1

公开(公告)日：2018-12-13

申请号：US16002534

申请日：2018-06-07

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F9/30

Abstract: A processing system includes a processing unit; a non-volatile memory storing configuration data; and a configuration data client including a register, wherein the configuration data client is configured to receive the configuration data and store the configuration data in the register. The processing system further includes a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data, read from the non-volatile memory, to the configuration data client. The hardware configuration circuit may be configured to receive a command, including an access request, from the processing unit and selectively execute the access request.

公开(公告)号：US20150192983A1

公开(公告)日：2015-07-09

申请号：US14591779

申请日：2015-01-07

Applicant: STMicroelectronics Application GmbH

Inventor： Fred Rennig

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3209 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3293 ,  H04L12/403 ,  Y02D10/10

Abstract: A bus microcontroller includes a processor circuit having at least one unit designed for performing one or more functions due to a bus command via a communication bus, a power control circuit adapted to be coupled to a transmitter-receiver circuit for receiving bus messages via the communication bus, and a means for placing at least part of the processor circuit into a reduced-power operating mode without placing the entire processor circuit into the reduced-power operating mode. The power control circuit is designed to evaluate incoming bus messages with respect to an activation bus message containing information on activating at least part of the processor circuit, and to output a corresponding activation control signal. The bus microcontroller also includes means for activating at least a part of the processor circuit that is placed in a reduced-power operating mode, in response to output of an activation control signal of the power control circuit.

Abstract translation: 总线微控制器包括具有至少一个单元的处理器电路，该至少一个单元被设计用于通过通信总线由总线命令执行一个或多个功能;功率控制电路，适于耦合到发送器 - 接收器电路，用于经由通信接收总线消息 总线，以及用于将处理器电路的至少一部分放置在降低功率操作模式而不使整个处理器电路进入降低功率操作模式的手段。 功率控制电路被设计为针对包含关于激活至少部分处理器电路的信息的激活总线消息来评估输入总线消息，并且输出相应的激活控制信号。 总线微控制器还包括用于响应于功率控制电路的激活控制信号的输出而激活放置在降低功率工作模式的处理器电路的至少一部分的装置。

公开(公告)号：US12190120B2

公开(公告)日：2025-01-07

申请号：US18312237

申请日：2023-05-04

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Roberto Colombo

IPC: G06F9/4401 ,  G06F21/64

Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.

公开(公告)号：US12061530B2

公开(公告)日：2024-08-13

申请号：US17655103

申请日：2022-03-16

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G06F11/22 ,  G06F11/07 ,  G06F11/273

CPC classification number: G06F11/2273 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/2733

Abstract: A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.

公开(公告)号：US20240171424A1

公开(公告)日：2024-05-23

申请号：US18509618

申请日：2023-11-15

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH ,  STMicroelectronics (Alps) SAS

Inventor： Fred Rennig ,  Giovanni Luca Torrisi ,  Manuel Gaertner ,  Philippe Sirito-Olivier ,  Fritz Burkhardt ,  Aldo Occhipinti

IPC: H04L12/40

CPC classification number: H04L12/40006 ,  H04L2012/40215

Abstract: A vehicle communication network includes electronic control units arranged in a plurality of groups. The electronic control units pertaining to the same group are coupled to each other via a respective dedicated communication bus. A central controller is coupled to the plurality of local controllers. Electrical loads are coupled to one of the electronic control units. Each of the electronic control units is configured to decode the received CAN frame to produce the actuation signal for a respective electrical load in response to a CAN frame being received from the respective local controller and transmit a CAN wake-up frame to the respective local controller and encode the feedback signal into a CAN frame for transmission to the respective local controller in response to the feedback signal being received from the respective electrical load.

公开(公告)号：US20240160598A1

公开(公告)日：2024-05-16

申请号：US18503744

申请日：2023-11-07

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Mirko Dondini ,  Calogero Andrea Trecarichi ,  Fred Rennig

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/40

Abstract: An example processing system includes a processing circuit, a volatile memory and a CAN communication controller circuit. The CAN communication controller circuit includes configuration and status registers. A transmission handler circuit and a reception handler circuit transmits and receives data via the CAN core circuit by exchanging data with the volatile memory based on the configuration data stored to the configuration and status registers, and filter elements stored to the volatile memory. Specifically, the processing system further includes a hardware host circuit comprising a non-volatile memory configured to store first configuration data (CD1) and second configuration data (CD2). The CD1 includes configuration data to be transferred to the configuration and status registers of the CAN communication controller circuit and the CD2 includes at least one filter element to be transferred to the volatile memory. A control circuit manages an initialization mode, a reception mode and a transmission mode. During the initialization mode, the hardware host circuit stores the CD1 to the configuration and status registers and the CD2 to the volatile memory.

公开(公告)号：US11921910B2

公开(公告)日：2024-03-05

申请号：US17443497

申请日：2021-07-27

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio

IPC: G06F21/83 ,  G06F9/38 ,  G06F9/445 ,  G06F12/02 ,  G06F21/57 ,  G06F21/64 ,  G06F21/74 ,  G09C1/00 ,  H04L9/32 ,  H04L9/40 ,  H04W4/40 ,  H04W12/03 ,  H04W12/106 ,  H04W12/40

CPC classification number: G06F21/83 ,  G06F9/3816 ,  G06F9/445 ,  G06F12/02 ,  G06F21/57 ,  G06F21/64 ,  G06F21/74 ,  G09C1/00 ,  H04L9/3234 ,  H04W12/106 ,  G06F2212/7209 ,  H04L63/0853 ,  H04W4/40 ,  H04W12/03 ,  H04W12/40

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

公开(公告)号：US20240021604A1

公开(公告)日：2024-01-18

申请号：US18478465

申请日：2023-09-29

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMICROELECTRONICS (TOURS) SAS

Inventor： Mathieu ROUVIERE ,  Arnaud YVON ,  Mohamed SAADNA ,  Vladimir SCARPA

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/872

CPC classification number: H01L27/0629 ,  H01L21/0254 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/872

Abstract: A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.