公开(公告)号：KR1020150141240A

公开(公告)日：2015-12-18

申请号：KR1020140069369

申请日：2014-06-09

Applicant: 삼성전자주식회사

Inventor： 서보영 ,  이용규 ,  전기문

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/8247

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/08 ,  H01L27/11507 ,  H01L27/11509

Abstract: 가변저항메모리소자들을포함하는반도체메모리장치가제공된다. 반도체기판상에서제 1 높이에배치된제 1 비트라인, 상기반도체기판상에서상기제 1 높이와다른제 2 높이에배치되는제 2 비트라인, 상기제 1 비트라인과연결되는제 1 가변저항메모리소자, 및상기제 2 비트라인과연결되는제 2 가변저항메모리소자를포함하되, 상기제 1 및제 2 가변저항메모리소자들은상기반도체기판으로부터실질적으로동일한높이에배치될수 있다.

Abstract translation: 提供了包括可变电阻存储器件的半导体存储器件。 半导体存储器件包括：第一位线，其布置在半导体衬底上的第一高度; 第二位线布置在与半导体衬底上的第一高度不同的第二高度处; 连接到第一位线的第一可变电阻存储器件; 以及连接到第二位线的第二可变电阻存储器件。 第一和第二可变电阻存储器件可以布置在与半导体衬底实际相同的高度处。

公开(公告)号：KR1020140113220A

公开(公告)日：2014-09-24

申请号：KR1020130028336

申请日：2013-03-15

Applicant: 삼성전자주식회사

Inventor： 이동한 ,  최성후 ,  공재섭 ,  윤성철 ,  전기문

IPC: G06F1/00 ,  G06F1/04 ,  G06F1/32

CPC classification number: G09G5/363 ,  G09G5/18 ,  G09G2330/021 ,  G09G2352/00 ,  G09G2360/06

Abstract: A multimedia system according to an embodiment of the present invention comprises a main special function register (SFR) saving SFR information; multiple processing modules, each of which processes each frame of data based on the SFR information; and a system control logic controlling the main SFR and the operation of the multiple processing modules. Each of the multiple processing modules can concurrently process different frames of data.

Abstract translation: 根据本发明的实施例的多媒体系统包括：保存SFR信息的主特殊功能寄存器（SFR）; 多个处理模块，每个处理模块基于SFR信息处理每个数据帧; 以及控制主SFR和多个处理模块的操作的系统控制逻辑。 多个处理模块中的每一个可以同时处理不同的数据帧。

公开(公告)号：KR1020140075436A

公开(公告)日：2014-06-19

申请号：KR1020120143770

申请日：2012-12-11

Applicant: 삼성전자주식회사

Inventor： 이동한 ,  강은지 ,  공재섭 ,  전기문

IPC: G06F9/06 ,  G06F13/14

CPC classification number: G11C29/023 ,  G11C11/5642

Abstract: An SoC including a special function register and an operation method thereof are provided. The special function register includes a first update storage unit, a second update storage unit, a first update logic corresponding to the first update storage unit, and a second update logic corresponding to the second update storage unit. When the first update logic is enabled, a clock is provided to the first update storage unit. When the second logic is enabled, a clock is provided to the second update storage unit.

Abstract translation: 提供了包括特殊功能寄存器及其操作方法的SoC。 特殊功能寄存器包括第一更新存储单元，第二更新存储单元，对应于第一更新存储单元的第一更新逻辑以及对应于第二更新存储单元的第二更新逻辑。 当启用第一更新逻辑时，向第一更新存储单元提供时钟。 当启用第二逻辑时，向第二更新存储单元提供时钟。

公开(公告)号：KR1020140040933A

公开(公告)日：2014-04-04

申请号：KR1020120107589

申请日：2012-09-27

Applicant: 삼성전자주식회사

Inventor： 김수용 ,  김주환 ,  허준호 ,  전기문

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: Disclosed are a system-on-chip (SoC) and an operation method thereof. The operation method of an SoC connected between multiple intellectual properties (IPs) and a memory device includes the steps of: monitoring whether a data transaction occurs between one or more IPs of the multiple IPs and the memory device; determining the operation status of each IP based on the result of the monitoring; and supplying the power corresponding to the operation status determined for each IP.

Abstract translation: 公开了一种片上系统（SoC）及其操作方法。 连接在多个知识产权（IP）和存储设备之间的SoC的操作方法包括以下步骤：监视在多个IP的一个或多个IP与存储设备之间是否发生数据事务; 根据监测结果确定每个IP的运行状况; 并且提供与为每个IP确定的操作状态相对应的功率。

公开(公告)号：KR1020020078885A

公开(公告)日：2002-10-19

申请号：KR1020010019154

申请日：2001-04-11

Applicant: 삼성전자주식회사

Inventor： 전기문

IPC: H01L21/28

Abstract: PURPOSE: A method for fabricating a via contact of a semiconductor device is provided to prevent a void inside a via hole by basically preventing outgasing source from being radiated by transformation of a low dielectric layer. CONSTITUTION: A metal interconnection in which barrier metal layers(202a,202b) are placed on and under a metal layer(204) is formed on an insulated substrate(200). The first insulation layer(206) of a low dielectric constant is formed on the substrate. The second insulation layer(208) of a chemical vapor deposition(CVD) layer material is formed on the first insulation layer. A chemical mechanical polishing(CMP) process is performed regarding the second insulation layer to planarize the second insulation layer. The second and first insulation layers are sequentially etched to form a wide hole so that the metal interconnection is partially exposed. The third insulation layer(210) of a CVD layer material is filled in the wide hole. The third insulation layer is etched to form the via hole by using a resist pattern for defining a via hole formation part so that the meal interconnection in the wide hole is exposed. An ashing process and a wet strip process are performed. A barrier metal layer is interposed on the resultant structure to form a conductive layer so that the inside of the via hole is sufficiently filled. A CMP process is performed on the barrier metal layer to expose the second insulation layer so that a conductive plug is formed in the via hole.

Abstract translation: 目的：提供一种用于制造半导体器件的通孔接触的方法，用于通过基本上防止通过低介电层的变换辐射源而使通孔内的空隙。 构成：在绝缘基板（200）上形成有金属层（202a，202b）放置在金属层（204）上和下方的金属互连。 在基板上形成低介电常数的第一绝缘层（206）。 化学气相沉积（CVD）层材料的第二绝缘层（208）形成在第一绝缘层上。 对第二绝缘层进行化学机械抛光（CMP）工艺以使第二绝缘层平坦化。 依次蚀刻第二和第一绝缘层以形成宽孔，使金属互连部分露出。 CVD层材料的第三绝缘层（210）填充在宽孔中。 通过使用用于限定通孔形成部分的抗蚀剂图案来蚀刻第三绝缘层以形成通孔，使得广角孔中的餐具互连被暴露。 执行灰化处理和湿条进程。 在所得到的结构上插入阻挡金属层，以形成导电层，使得通孔的内部被充分地填充。 在阻挡金属层上进行CMP工艺以暴露第二绝缘层，使得在通孔中形成导电插塞。

公开(公告)号：KR1020020022232A

公开(公告)日：2002-03-27

申请号：KR1020000054932

申请日：2000-09-19

Applicant: 삼성전자주식회사

Inventor： 전기문

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: PURPOSE: A wafer having a plurality of monitor patterns in one scribe line is provided to minimize a process defect of each semiconductor chip, by forming the monitor patterns without increasing the area of the scribe line surrounding a semiconductor chip. CONSTITUTION: At least one monitoring pattern for the first semiconductor chip and at least one monitoring pattern for the second semiconductor chip are formed in the scribe line to monitor the characteristic of the first and second semiconductor chips fabricated by using the scribe line as a boundary. The monitoring patterns for the first and second semiconductor chips do not overlap each other.

Abstract translation: 目的：提供在一个划线中具有多个监视器图案的晶片，通过在不增加围绕半导体芯片的划线的面积的情况下形成监视器图案来最小化每个半导体芯片的工艺缺陷。 构成：在划线中形成用于第一半导体芯片的至少一个监测图案和用于第二半导体芯片的至少一个监测图案，以监测通过使用划线作为边界制造的第一和第二半导体芯片的特性。 第一和第二半导体芯片的监视模式彼此不重叠。