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Patent Agency Ranking
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公开(公告)号：KR1019950012578B1
公开(公告)日：1995-10-19
申请号：KR1019920026055
申请日：1992-12-29
IPC: H04L7/02
Abstract: an edge detecting unit for generating a change pulse showing a change in data by detecting a raising and dropping point of a digital reception signal to be randomly inputted from outside; a counting unit for counting a phase value of a present signal after counting it from a point of generating the change of the input signal by inputting the change pulse from the edge detecting unit; a phase comparison and control unit for receiving the phase value of a signal generated from the counting unit, comparing the phase difference between the two input signals, and outputting a control pulse to be used for compensating the phase; and a data clock generating and dividing unit for receiving the control pulse and the reception signal, generating a data clock synchronized with the reception signal under control of the phase comparison and control unit, outputting the synchronized reception signal and data clock to the outside, and providing the data clock to the phase comparison and control unit.
Abstract translation: 边缘检测单元，用于通过检测从外部随机输入的数字接收信号的上升点来产生表示数据变化的变化脉冲; 计数单元，用于通过从边缘检测单元输入改变脉冲从产生输入信号的变化的点对其进行计数之后，对当前信号的相位值进行计数; 相位比较和控制单元，用于接收从计数单元产生的信号的相位值，比较两个输入信号之间的相位差，并输出用于补偿相位的控制脉冲; 以及数据时钟生成和分割单元，用于接收控制脉冲和接收信号，在相位比较和控制单元的控制下产生与接收信号同步的数据时钟，将同步的接收信号和数据时钟输出到外部，以及 向相位比较和控制单元提供数据时钟。
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公开(公告)号：KR1019950011034B1
公开(公告)日：1995-09-27
申请号：KR1019930014784
申请日：1993-07-30
Applicant: 한국전자통신연구원
IPC: H03K19/21
Abstract: The Boolean Function Formula is implemented by a memory so that algorithm can be changed easily. The circuit comprises a MLSRs(23-25) for shifting input signals(D0,D1,D2), a CPU(22) for generating write enable, read enable, data and address signals, and a SRAM(21) for generating random number series according to expected number stored in the SRAM , output signals of the MLSR and address signal from the CPU.
Abstract translation: 布尔函数公式由存储器实现，从而可以轻松地更改算法。 电路包括用于移位输入信号（D0，D1，D2）的MLSR（23-25），用于产生写使能，读使能，数据和地址信号的CPU（22），以及用于产生随机数的SRAM 根据存储在SRAM中的预期数字序列，MLSR的输出信号和来自CPU的地址信号。
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公开(公告)号：KR1019950009421B1
公开(公告)日：1995-08-22
申请号：KR1019930019211
申请日：1993-09-21
Applicant: 한국전자통신연구원
IPC: H04L1/00
Abstract: The signal shaping circuit eliminates the intersymbol interference and jitter by suppressing the high frequency components from the transmitted signal. The device comprises a control unit(21) for generating address and control signal to prohibit the counting error of the external clock; a lookup table(22) for generating the digital data for the sinusoidal input; a D/A converter(23) for generating analog and DC signal of a specific level by using the lookup table(22) output.
Abstract translation: 信号整形电路通过抑制来自发射信号的高频分量来消除码间干扰和抖动。 该装置包括用于产生地址和控制信号以禁止外部时钟的计数误差的控制单元（21） 用于产生用于正弦输入的数字数据的查找表（22）; 用于通过使用查找表（22）输出产生特定电平的模拟和DC信号的D / A转换器（23）。
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