公开(公告)号：WO1993017350A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001800

申请日：1993-02-26

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  BROKAW, Paul, A.

IPC: G01R31/02

CPC classification number: G01R19/32

Abstract: An integrated circuit including a comparator having two output states and being responsive to a voltage developed across a shunt in the circuit so that the comparator assumes one of its two output states when the voltage developed across the shunt is greater than a threshold switching voltage and the other of its two output states when the voltage developed across the shunt is less than the threshold switching voltage. The integrated circuit additionally includes a threshold switching voltage sensitivity control circuit, coupled to and controlling the comparator, for controlling a sensitivity of the threshold switching voltage to changes in a supply voltage of the lamp circuit and for controlling a sensitivity of the threshold switching voltage to changes in temperature of the integrated circuit.

Abstract translation: 一种集成电路，包括具有两个输出状态的比较器，并且响应于在电路中的分流电路上产生的电压，使得当跨分流器产生的电压大于阈值开关电压时，比较器采用其两个输出状态之一， 当分流器上产生的电压小于阈值开关电压时，其两个输出状态中的另一个。 集成电路还包括耦合到和控制比较器的阈值切换电压灵敏度控制电路，用于控制阈值切换电压对灯电路的电源电压变化的灵敏度，并且用于控制阈值切换电压的灵敏度 集成电路的温度变化。

公开(公告)号：WO1991016766A1

公开(公告)日：1991-10-31

申请号：PCT/US1991002865

申请日：1991-04-25

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  BULZACHELLI, John, F.

IPC: H03L07/081

CPC classification number: H04L7/033 ,  H03L7/081 ,  H04L7/0029

Abstract: A voltage-controlled delay (418) is connected in series with a phase-locked loop (430). The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter (410). With this arrangement, the amplifier and filter can be designed to have a transfer function that does not include an explicit zero. Consequently, the jitter transfer function of the overall structure can be designed to remain equal to or less than unity over all frequencies and jitter peaking is eliminated.

公开(公告)号：WO1990000836A1

公开(公告)日：1990-01-25

申请号：PCT/US1989000783

申请日：1989-02-27

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MALLINSON, A., Martin

IPC: H03M03/02

CPC classification number: H03M3/02

Abstract: A delta modulator includes an integrator (12), a comparator (14) for sensing the output of the integrator and a flip flop (16) for synchronizing the comparator output to a clock signal and providing an error signal to the input of the integrator. The output (20) of the delta modulator is a data stream having a time-averaged duty cycle that represents the input signal amplitude. The integrator includes an amplifier (38) that is provided with positive feedback. Error caused by the finite open loop gain of the amplifier is cancelled by the positive feedback. As a result, high accuracy is achieved. The integrator amplifier is stabilised by the overall negative feedback of the delta modulator loop.

公开(公告)号：WO1989007792A1

公开(公告)日：1989-08-24

申请号：PCT/US1989000327

申请日：1989-01-26

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  BROKAW, A., Paul

IPC: G05F03/26

CPC classification number: G05F3/267

Abstract: A circuit which employs a pair of MOS transistors operating at equal gate and sources voltages, and nearly equal drain voltages, to produce an accurately ratioed current mirror. The gate voltage of the transistor pair is controlled by a simple current mirror operating at a small fraction of the total output. The latter current mirror also functions as a wideband negative impedance converter. A comparable bipolar circuit is also discussed.

公开(公告)号：WO1988009034A2

公开(公告)日：1988-11-17

申请号：PCT/US1987003277

申请日：1987-12-10

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GARDE, Douglas

IPC: G11C07/06

CPC classification number: G11C7/062 ,  H03K5/2481

Abstract: A MOS sense amplifier having a differential input and a single-ended output, and formed of only six MOS transistors. The amplifier's non-inverting input is connected to the gates of first and second MOSFETs. The drains of the first and second MOSFETs are connected to each other and to the gates of third and fourth MOSFETs. The drain of the third MOSFET is connected to the sources of the second and sixth MOSFETs; and the source of the third MOSFET is connected to the positive supply voltage. The drain of the fourth MOSFET is connected to the sources of the first and fifth MOSFETs. The source of the fourth MOSFET is connected to ground. The inverting input of the sense amplifier is connected to the gates of the fifth and sixth MOSFETs. The drains of the fifth and sixth MOSFETs are connected to each other and provide the output terminus of the amplifier. The first, fourth and fifth MOSFETs are n-channel devices, while the second, third and sixth MOSFETs are p-channel devices.

Abstract translation: 具有差分输入和单端输出的MOS读出放大器，仅由六个MOS晶体管构成。 放大器的非反相输入端连接到第一和第二MOSFET的栅极。 第一和第二MOSFET的漏极彼此连接并连接到第三和第四MOSFET的栅极。 第三MOSFET的漏极连接到第二和第六MOSFET的源极; 并且第三个MOSFET的源极连接到正电源电压。 第四个MOSFET的漏极连接到第一和第五个MOSFET的源极。 第四个MOSFET的源极接地。 读出放大器的反相输入连接到第五和第六个MOSFET的栅极。 第五和第六个MOSFET的漏极相互连接并提供放大器的输出端。 第一，第四和第五MOSFET是n沟道器件，而第二，第三和第六MOSFET是p沟道器件。

公开(公告)号：WO1986004700A1

公开(公告)日：1986-08-14

申请号：PCT/US1986000243

申请日：1986-02-04

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GARDE, Douglas

IPC: G06F09/22

CPC classification number: G06F9/223 ,  G06F9/3869

Abstract: A microprogrammed controller (10) wherein the conventional pipeline register is replaced by a pair of coupled latches: a so-called ''transparent'' latch (30) is placed between the output of the microprogram memory (12) and the input of one or more system resources including at least the sequencer (16) or address generator (20), and another latch (32, 34) is placed between the output of each such resource and the element(s) to be supplied with its output. The appropriate bits of a microinstruction are supplied from the microinstruction memory (12) to the associated resource via the transparent latch (30). The clock signal for the sequencer or other resource serves as the enable signal for the output latch (32, 34) (which can be either a transparent latch or an edge-triggered latch responsive to the rising edge of the clock signal), while the inverted sense of the clock signal provides the enable signal for the transparent latch (30). This allows data to propagate through the resource to internal destinations therein even before the results of the previous instruction are cleared from the resource's output latch. Set-up conditions for an instruction thus can occur within a resource while the results of the previous instruction are still sitting in the resource's output latch. Therefore those set-up conditions can already have been completed (or at least partially completed) before the results of the prior instruction are cleared out of the output latch and the new microinstruction is latched into the input latch.

Abstract translation: 一个微程序控制器（10），其中常规流水线寄存器由一对耦合的锁存器代替：所谓的“透明”锁存器（30）被放置在微程序存储器（12）的输出端和一个输入端 或更多的系统资源，包括至少定序器（16）或地址生成器（20），并且另一个锁存器（32,34）被放置在每个这样的资源的输出和要被提供其输出的元件之间。 微指令的适当位通过透明锁存器（30）从微指令存储器（12）提供给相关资源。 定序器或其他资源的时钟信号用作输出锁存器（32,34）的使能信号（可以是响应于时钟信号的上升沿的透明锁存器或边沿触发锁存器），而 时钟信号的反相感测为透明锁存器（30）提供使能信号。 即使在从资源的输出锁存器清除先前指令的结果之前，这也允许数据通过资源传播到内部目的地。 因此，指令的设置条件可以发生在资源内，而先前指令的结果仍然位于资源的输出锁存器中。 因此，在先前指令的结果从输出锁存器中清除之前，这些设置条件可能已经完成（或至少部分完成），并且新的微指令被锁存到输入锁存器中。

公开(公告)号：WO1998015054A1

公开(公告)日：1998-04-09

申请号：PCT/US1997018347

申请日：1997-10-03

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  SZEPESI, Thomas, S. ,  BUXTON, Joseph, C. ,  ZANSKY, Zolton ,  BOWERS, Derek, F.

IPC: H03F03/45

CPC classification number: G05F3/222 ,  H03F3/211 ,  H03F3/45071

Abstract: Operational transconductance amplifiers (OTAs) (10, 12) are combined at their outputs, yielding a single frequency compensation connection point (16). In a preferred embodiment, the output of each OTA is asymmetric, i.e., they can only source current and the OTA outputs are tied together to a constant current sink (14). Consequently, the OTA that sources more current controls the voltage of the merged output. This merged output point provides a voltage output that may be used as a frequency compensation point.

Abstract translation: 操作跨导放大器（ODA）（10,12）在其输出端被组合，产生单个频率补偿连接点（16）。 在优选实施例中，每个OTA的输出是不对称的，即，它们只能源电流，并且OTA输出被连接到恒定电流吸收器（14）。 因此，来自更多电流的OTA控制合并输出的电压。 该合并输出点提供可用作频率补偿点的电压输出。

公开(公告)号：WO1998008298A1

公开(公告)日：1998-02-26

申请号：PCT/US1997014474

申请日：1997-08-18

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  COLN, Michael, C. ,  NESTLER, Eric

IPC: H03B19/00

CPC classification number: H03C3/00 ,  H03B28/00 ,  H03M1/86

Abstract: A voltage-to-frequency converter having an analog-to-digital converter (22), based on analog components, for converting samples of an analog signal (Vin) into corresponding digital words and a digital-to-frequency (26), based on digital components (28, 30, 34), for converting the digital words into a train of pulses having a pulse repetition frequency related to the analog voltage (Vin). An interpolator (24) is provided between the analog-to-digital converter and the digital-to-frequency converter for providing digital words for the digital-to-frequency converter at a rate greater than the operating rate of the analog-to-digital converter.

Abstract translation: 一种具有基于模拟部件的模数转换器（22）的电压 - 频率转换器（22），用于将模拟信号（Vin）的采样转换成相应的数字字和基于数字频率（26）的样本 在数字组件（28,30,34）上，用于将数字字转换为具有与模拟电压（Vin）相关的脉冲重复频率的脉冲串。 在模数转换器和数 - 频转换器之间提供了一个内插器（24），用于以大于模 - 数转换器的工作速率的数字 - 频率转换器提供数字字 转换器。

公开(公告)号：WO1997050188A1

公开(公告)日：1997-12-31

申请号：PCT/US1997009812

申请日：1997-06-10

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  RIBNER, David, Byrd ,  ROBERTSON, David, Hall

IPC: H04B01/38

CPC classification number: H04L5/143 ,  H04L5/023

Abstract: A discrete multi-tone, asymmetrical transceiver (10') and method wherein a modem at a central office (12') transmits information to a modem at a remote terminal (14') on a down-stream signal and the modem at the remote terminal (14') transmits information to the modem at the central office (12') on an up-stream signal. The up-stream signal comprises data carried by a lower portion of a predetermined band of frequencies and the down-stream signal comprises data carried by an upper portion of the predetermined band of frequencies.

Abstract translation: 一种离散的多音调非对称收发机（10'）和方法，其中中心局（12'）上的调制解调器向下行信号的远程终端（14'）向远程终端（14'）的调制解调器发送信息，并且远程 终端（14'）在上行信号上向中心局（12'）向调制解调器发送信息。 上行信号包括由预定频带的较低部分承载的数据，并且下行流信号包括由预定频带的上部承载的数据。

公开(公告)号：WO1997043833A1

公开(公告)日：1997-11-20

申请号：PCT/IB1997000825

申请日：1997-05-13

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  DEMPSEY, Dennis, A. ,  TUTHILL, Michael, Gerard ,  COTTER, Martin, Gerard

IPC: H03M01/06

CPC classification number: H03M1/0602 ,  H03M1/785

Abstract: A switch architecture for a digital-to-analog converter provides improved linearity. A first switch for one leg of the R/2R resistance ladder includes a unit resistor coupled between the MOSFET devices of the switch and the respective leg of the R/2R ladder. The on resistances of the MOSFET devices of the first switch are controlled in response to a reference value, such as the resistance of a reference resistor, which may have a resistance and other characteristics similar to the unit resistor. Other switches for other legs of the R/2R ladder also have a unit resistor, or other MOSFET devices having an on resistance controlled in relation to the reference value. Additional switches for other legs of the R/2R ladder may also have MOSFET devices of varying width to channel (W/L) ratios. Each of these approaches may be combined to achieve a binary weighting or an alternate weighting between legs of the R/2R ladder, in order to provide low linearity error.

Abstract translation: 用于数模转换器的开关架构提供了改进的线性度。 R / 2R电阻梯的一条支脚的第一开关包括耦合在开关的MOSFET器件和R / 2R梯的相应支路之间的单元电阻器。 第一开关的MOSFET器件的导通电阻响应于诸如参考电阻器的电阻的参考值来控制，其可以具有与单元电阻器类似的电阻和其它特性。 R / 2R梯子的其他支路的其他开关也具有单位电阻器或具有相对于参考值控制的导通电阻的其它MOSFET器件。 R / 2R梯形图的其他支脚的附加开关也可以具有宽度与沟道（W / L）比率变化的MOSFET器件。 这些方法中的每一种可以组合以实现R / 2R梯级的支路之间的二进制加权或者交替加权，以便提供低线性误差。