公开(公告)号：WO2014089155A1

公开(公告)日：2014-06-12

申请号：PCT/US2013/073011

申请日：2013-12-04

Applicant: ANALOG DEVICES, INC.

Inventor： NESTLER, Eric ,  CASTRO, Gustavo

IPC: H03H15/02 ,  H03H19/00

CPC classification number: H03H15/02 ,  H03H19/004

Abstract: A filter provides high-pass coupling between circuits. The filter includes charge storage elements and switch elements coupling the charge storage elements. A controller is coupled to the switch elements for sequencing configurations of the switch elements in phases for each of a succession of sample periods to perform a time sampled continuous value signal processing of the input signal to form the processed signal. The sequenced configurations include a configuration in which a charge representing a value of the input signal is stored on a multiple of the charge storage elements, a configuration in which charge storage elements are coupled with the switch elements, and a set of one or more configurations that implement a scaling of a charge on one of the charge storage elements to be on one or more of the charge storage elements.

Abstract translation: 滤波器提供电路之间的高通耦合。 滤波器包括电荷存储元件和耦合电荷存储元件的开关元件。 控制器耦合到开关元件，用于对开关元件的配置进行排序，以对于连续的采样周期中的每一个进行相位，以执行输入信号的时间采样连续值信号处理以形成处理的信号。 顺序配置包括其中表示输入信号的值的电荷存储在电荷存储元件的倍数上的配置，其中电荷存储元件与开关元件耦合的配置，以及一组一个或多个配置 其中一个电荷存储元件上的电荷在一个或多个电荷存储元件上实现。

公开(公告)号：WO1998008298A1

公开(公告)日：1998-02-26

申请号：PCT/US1997014474

申请日：1997-08-18

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  COLN, Michael, C. ,  NESTLER, Eric

IPC: H03B19/00

CPC classification number: H03C3/00 ,  H03B28/00 ,  H03M1/86

Abstract: A voltage-to-frequency converter having an analog-to-digital converter (22), based on analog components, for converting samples of an analog signal (Vin) into corresponding digital words and a digital-to-frequency (26), based on digital components (28, 30, 34), for converting the digital words into a train of pulses having a pulse repetition frequency related to the analog voltage (Vin). An interpolator (24) is provided between the analog-to-digital converter and the digital-to-frequency converter for providing digital words for the digital-to-frequency converter at a rate greater than the operating rate of the analog-to-digital converter.

Abstract translation: 一种具有基于模拟部件的模数转换器（22）的电压 - 频率转换器（22），用于将模拟信号（Vin）的采样转换成相应的数字字和基于数字频率（26）的样本 在数字组件（28,30,34）上，用于将数字字转换为具有与模拟电压（Vin）相关的脉冲重复频率的脉冲串。 在模数转换器和数 - 频转换器之间提供了一个内插器（24），用于以大于模 - 数转换器的工作速率的数字 - 频率转换器提供数字字 转换器。

公开(公告)号：WO2004077677A1

公开(公告)日：2004-09-10

申请号：PCT/US2004/005409

申请日：2004-02-24

Applicant: ANALOG DEVICES, INC.

Inventor： NESTLER, Eric ,  DAIGLE, Paul ,  ASHBURN, Michael, A., Jr.

IPC: H03M1/12

CPC classification number: H03M1/124

Abstract: An analog-to-digital metering circuit (100 of Figure 2) includes a first programmable gain amplifier (110 of Figure 2) to amplify a first voltage signal from a first channel before being received by a first analog-to-digital converter (115 of Figure 2) that converts the amplified first voltage signal to a first digital signal. A second programmable gain amplifier (120 of Figure 2) amplifies a second voltage signal from a second channel and feds the amplified signal to a second analog-to-digital converter (125 of Figure 2) that converts the amplified second voltage signal to a second digital signal. A first lowpass filter circuit (142 of Figure 2) receives the first and second digital signals to generate, therefrom, a multi-bit analog-to-digital value. A direct digital synthesizer (152 of Figure 2) generates a digital signal representing a predetermined waveform that is fed to a digital-to-analog converter (130 of Figure 2). The second voltage signal and the digital signal representing the predetermined waveform are multiplied together to generate a digital value. Phase shifting circuitry (148 of Figure 2) provides a signal representing a 90-degree phase shift of the digital value and a signal representing a 0-degree phase shift of the digital value. RMS circuitry (158 & 160 of Figure 2) converts the 0-degree phase digital signal into an In-Phase signal and the 90-degree phase digital signal into a Quadrature signal.

Abstract translation: 模拟数字计量电路（图2中的100）包括第一可编程增益放大器（图2中的110），以在由第一模数转换器（115）接收之前放大来自第一通道的第一电压信号 的图2），其将放大的第一电压信号转换为第一数字信号。 第二可编程增益放大器（图2的120）放大来自第二通道的第二电压信号，并将放大的信号调制到第二模数转换器（图2的125），该第二模数转换器将放大的第二电压信号转换为第二 数字信号。 第一低通滤波器电路（图2的142）接收第一和第二数字信号，从而产生多比特模数值。 直接数字合成器（图2的152）产生表示被馈送到数模转换器（图2的130）的预定波形的数字信号。 将表示预定波形的第二电压信号和数字信号相乘以产生数字值。 相移电路（图2的148）提供表示数字值的90度相移的信号和表示数字值的0度相移的信号。 RMS电路（图2的158和160）将0度相位数字信号转换为同相信号，将90度相位数字信号转换成正交信号。

公开(公告)号：WO2012170533A2

公开(公告)日：2012-12-13

申请号：PCT/US2012/041101

申请日：2012-06-06

Applicant: ANALOG DEVICES, INC. ,  NESTLER, Eric ,  VENUTI, Jeffrey ,  ZLATKOVIC, Vladimir ,  NANDA, Kartik

Inventor： NESTLER, Eric ,  VENUTI, Jeffrey ,  ZLATKOVIC, Vladimir ,  NANDA, Kartik

IPC: H03H7/00

CPC classification number: H03K5/00 ,  H03H15/02

Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

Abstract translation: 时域滤波方法采用无源电荷共享方式来实现无限脉冲响应滤波器。 将输入信号的延迟样本作为电荷存储在第一电容器阵列的电容器上，并且将输出信号的延迟采样作为电荷存储在第二电容器阵列的电容器上。 输出由第一和第二阵列的电容器彼此无源耦合确定，并根据耦合的电容器上的总电荷来确定输出。 在一些示例中，在将输出存储在第二电容器阵列之前，将增益应用于总电荷。 在一些示例中，在耦合电容器之前，将电荷量化电路应用于存储在阵列上的电荷以形成输出。

公开(公告)号：WO2012024507A2

公开(公告)日：2012-02-23

申请号：PCT/US2011/048278

申请日：2011-08-18

Applicant: ANALOG DEVICES, INC. ,  NESTLER, Eric ,  ZLATKOVIC, Vladimir ,  VENUTI, Jeffrey

Inventor： NESTLER, Eric ,  ZLATKOVIC, Vladimir ,  VENUTI, Jeffrey

IPC: H04R25/02

CPC classification number: H03H7/0138 ,  G06F17/5063 ,  G10K15/00 ,  H02M1/14 ,  H03H15/00 ,  H03H15/02 ,  H03M1/12 ,  H04R25/00

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract translation: 在一个方面，离散时间模拟信号处理模块的降低的功耗和/或电路面积是在利用完全或基本上使用无源电荷共享电路的方法中实现的，其可以包括 可配置的（例如，在制造之后，在运行时）倍增缩放级，其不需要信号路径中的有源器件。 在一些示例中，乘法系数被数字地表示，并且被变换以配置可重新配置电路以实现期望系数和电荷转移程度之间的线性关系。 在一些示例中，使用多个连续的电荷共享阶段来实现期望的乘法效应，其提供系数的大动态范围，而不需要电容元件的尺寸的相称范围。 缩放电路可以组合成可配置的时域或频域滤波器。

公开(公告)号：WO2002088761A2

公开(公告)日：2002-11-07

申请号：PCT/US2002/013256

申请日：2002-04-26

Applicant: ANALOG DEVICES, INC.

Inventor： NESTLER, Eric

IPC: G01R21/00

CPC classification number: G01R21/133 ,  G01R21/127

Abstract: A power metering system including a first modulator receiving a first analog voltage associated with a current and outputting a first digitized signal. A second modulator receives a second analog voltage and outputs a second digitized signal. A first lowpass filter filters out high frequency noise associated with the first signal and decimates the frequency of the first digitized signal. The first lowpass filter outputs a first filtered signal. An interpolator performs up sampling of the signal associated with the first filtered signal. The interpolator outputs a first up sampled signal. An integrator integrates the first up sampled signal. The integrator outputs an integrated signal. A first multiplier multiplies the second digitized signal and integrated signal, and outputs a multiplied signal. The multiplied signal being used to measure power.

Abstract translation: 一种电力计量系统，包括接收与电流相关联的第一模拟电压并输出第一数字化信号的第一调制器。 第二调制器接收第二模拟电压并输出第二数字化信号。 第一低通滤波器滤除与第一信号相关联的高频噪声并抽取第一数字化信号的频率。 第一个低通滤波器输出第一个滤波信号。 内插器执行与第一滤波信号相关联的信号的采样。 内插器输出第一上采样信号。 积分器集成了第一个上采样信号。 积分器输出积分信号。 第一乘法器将第二数字化信号和积分信号相乘，并输出相乘的信号。 倍增信号用于测量功率。

公开(公告)号：WO1998002838A1

公开(公告)日：1998-01-22

申请号：PCT/US1997012069

申请日：1997-07-11

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  NESTLER, Eric

IPC: G06J01/00

CPC classification number: G06J1/00

Abstract: An apparatus and a method for multiplying two time varying signals to produce a four quadrant, multiplied signal is provided. In one embodiment of the present invention, an apparatus for multiplying a first signal with a second signal includes an analog-to-digital converter that provides a first digital signal representative of the first signal, a first modulator that provides a first modulated signal representative of the second signal, a multiplier that multiplies that first digital signal by the first modulated signal and provides a second digital signal representative of a result of a multiplication of the first signal and the second signal, and a first filter having an input to receive the second digital signal and having an output that provides the multiplied signal.

Abstract translation: 提供了一种用于将两个时变信号相乘以产生四象限乘法信号的装置和方法。 在本发明的一个实施例中，一种用于将第一信号与第二信号相乘的装置包括提供表示第一信号的第一数字信号的模数转换器，提供表示第一信号的第一调制信号的第一调制器 所述第二信号是将所述第一数字信号乘以所述第一调制信号并提供代表所述第一信号和所述第二信号的相乘结果的第二数字信号的乘法器，以及具有用于接收所述第二信号的输入的第一滤波器 数字信号并具有提供相乘信号的输出。

公开(公告)号：EP3133737A1

公开(公告)日：2017-02-22

申请号：EP16188984.5

申请日：2011-08-18

Applicant: Analog Devices, Inc.

Inventor： NESTLER, Eric ,  ZLATKOVIC, Vladimir ,  VENUTI, Jeffrey

IPC: H03H7/00

CPC classification number: H03H7/0138 ,  G06F17/5063 ,  G10K15/00 ,  H02M1/14 ,  H03H15/00 ,  H03H15/02 ,  H03M1/12 ,  H04R25/00

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements.; The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract translation: 在一个方面，离散时间模拟信号处理模块的降低的功耗和/或电路面积是通过使用完全或很大程度上被动电荷共享电路的方法实现的，其中可能包括可配置（例如，在制造之后， 运行时）乘法缩放阶段，不需要信号路径中的有源设备。 在一些示例中，乘法系数被数字地表示，并且被变换以配置可重构电路以实现期望系数和电荷转移程度之间的线性关系。 在一些示例中，使用多个连续的电荷共享阶段来实现期望的乘法效应，其提供大的动态范围的系数，而不需要电容元件尺寸的相应范围; 缩放电路可以组合以形成可配置的时域或频域滤波器。

公开(公告)号：EP2584971A1

公开(公告)日：2013-05-01

申请号：EP11798920.2

申请日：2011-06-23

Applicant: Analog Devices, Inc.

Inventor： VIGODA, Benjamin ,  BERNSTEIN, Jeffrey ,  NESTLER, Eric

IPC: A61B8/00

CPC classification number: A61B8/4444 ,  A61B8/4472 ,  A61B8/4488 ,  A61B8/54 ,  G01S7/5202 ,  G01S7/5208 ,  G01S7/52082 ,  G01S7/52096 ,  G01S15/8909 ,  G01S15/8915 ,  G01S15/8927 ,  G10K11/346

Abstract: An approach to signal processing in an imaging system, for instance an ultrasound medical imaging system, makes use of analog signal processing prior to conversion to digital form, which may be performed in a portable probe of the system. In some examples, the system includes multiple controllable input processing blocks, each implementing a discrete time analog signal processing stage such as time domain filtering for fractional time delay, anti-alias filtering, or matched filtering. The processing blocks may be implemented using a passive charge sharing approach in which charge is transferred between capacitive elements in successive phases using controlled switches.

公开(公告)号：EP3133737B1

公开(公告)日：2019-05-01

申请号：EP16188984.5

申请日：2011-08-18

Applicant: Analog Devices, Inc.

Inventor： NESTLER, Eric ,  ZLATKOVIC, Vladimir ,  VENUTI, Jeffrey

IPC: H03H7/00