公开(公告)号：US20120325517A1

公开(公告)日：2012-12-27

申请号：US13168675

申请日：2011-06-24

Applicant: Cyprian Uzoh ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Craig Mitchell

IPC: H01B5/00 ,  H01B13/00

CPC classification number: H01B13/0036 ,  H01L24/43 ,  H01L24/45 ,  H01L2224/43 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/4516 ,  H01L2224/45163 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45605 ,  H01L2224/45609 ,  H01L2224/45611 ,  H01L2224/45644 ,  H01L2224/45647 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/4568 ,  H01L2224/45686 ,  H01L2224/45693 ,  H01L2224/45887 ,  H01L2224/45893 ,  H01L2224/48 ,  H01L2224/85207 ,  H01L2924/01015 ,  H01L2924/10253 ,  Y10T29/49117 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/01006

Abstract: A wire structure, which may be configured for a semiconductor device, is disclosed. The wire may include an elongate flexible core formed of a conductor material and a cladding layer covering an outer surface of the core. The cladding layer may be a conductor. In various aspects the cladding layer and core have a different grain sizes. An average grain size of the core material may several orders of magnitude greater than an average grain size of the cladding layer material. The cladding layer may be an alloy having a varying concentration of a minor component across its thickness. Methods of forming a wire structure are also disclosed.

Abstract translation: 公开了一种可被配置用于半导体器件的导线结构。 线可以包括由导体材料形成的细长柔性芯和覆盖芯的外表面的覆层。 包层可以是导体。 在各个方面，包覆层和芯具有不同的晶粒尺寸。 芯材的平均晶粒尺寸可以比包覆层材料的平均晶粒尺寸大几个数量级。 包覆层可以是在其厚度上具有不同浓度的次要组分的合金。 还公开了形成线结构的方法。

公开(公告)号：US20070135022A1

公开(公告)日：2007-06-14

申请号：US11704631

申请日：2007-02-09

Applicant: Bulent Basol ,  Cyprian Uzoh

Inventor： Bulent Basol ,  Cyprian Uzoh

IPC: B24B49/00

CPC classification number: B24B57/02 ,  B24B37/042 ,  C23C18/1617 ,  C23C18/38 ,  C25D7/123 ,  C25D21/04 ,  C25D21/18 ,  H01L21/2885

Abstract: The present invention provides an apparatus for wet processing of a conductive layer using a degassed process solution such as a degassed electrochemical deposition solution, a degassed electrochemical polishing solution, a degassed deposition solution, and a degassed cleaning solution. The technique includes degassing the process solution before delivering the degassed process solution to a processing unit or degassing the process solution in situ, within the processing unit.

Abstract translation: 本发明提供一种使用脱气的电解沉积溶液，脱气电化学抛光溶液，脱气沉积溶液和脱气清洗溶液等脱气工艺溶液对导电层进行湿法加工的设备。 该技术包括在将脱气的处理溶液递送到处理单元之前对处理溶液进行脱气或在处理单元内原位脱气处理溶液。

公开(公告)号：US20060009033A1

公开(公告)日：2006-01-12

申请号：US11226511

申请日：2005-09-13

Applicant: Bulent Basol ,  Cyprian Uzoh

Inventor： Bulent Basol ,  Cyprian Uzoh

IPC: H01L21/461 ,  C25D17/00

CPC classification number: C25D17/001 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76877

Abstract: The process of the present invention forms copper interconnects in a semiconductor wafer surface. During the process, initially, narrow and large features are provided in the top surface of the wafer, and then a primary copper layer is deposited by employing an electrochemical deposition process. The primary copper layer completely fills the features and forms a planar surface over the narrow feature and a non-planar surface over the large feature. By employing an electrochemical mechanical deposition process, a secondary copper layer is deposited onto the primary copper layer to form a planar copper layer over the narrow and large features. After this process step, the thickness of the planar copper layer is reduced using an electropolishing process.

Abstract translation: 本发明的方法在半导体晶片表面中形成铜互连。 在该过程中，最初，在晶片的顶表面中提供窄且大的特征，然后通过使用电化学沉积工艺沉积初级铜层。 初级铜层完全填满了特征，并在狭窄的特征上形成一个平坦的表面，在大的特征上形成一个非平面的表面。 通过采用电化学机械沉积工艺，将二次铜层沉积在初级铜层上，以形成窄和大特征上的平面铜层。 在该工艺步骤之后，使用电解抛光工艺来减小平面铜层的厚度。

公开(公告)号：US20060006060A1

公开(公告)日：2006-01-12

申请号：US11225913

申请日：2005-09-13

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: C25D17/00

CPC classification number: C25D5/02 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76877

Abstract: An apparatus for processing a material on a surface of a wafer having a diameter includes a cavity defined by a peripheral wall terminating at a peripheral edge and having at least one lateral dimension smaller than the wafer diameter and at least one lateral dimension larger than the wafer diameter and configured to hold a process solution proximate to the peripheral edge such that the process solution will always contact a first wafer surface region, a head configured to hold the wafer above the cavity peripheral edge so that the surface of the wafer faces the cavity, and an electrical contact member positioned outside the cavity peripheral wall and configured to contact a second wafer surface region where the lateral dimension of the cavity is smaller than the wafer diameter and to maintain electrical contact with the wafer when the wafer is moved relative to the contact member. Advantages of the invention include substantially full surface treatment of the wafer.

Abstract translation: 一种用于处理具有直径的晶片表面上的材料的设备包括由外围壁限定的空腔，该外围壁终止于外围边缘并具有至少一个小于晶片直径的横向尺寸和至少一个大于晶片的横向尺寸 并且被配置为将处理溶液保持靠近外围边缘，使得处理溶液将始终接触第一晶片表面区域，头部被配置为将晶片保持在空腔周边边缘上方，使得晶片的表面面向空腔， 以及电接触构件，其定位在所述腔周壁外部并且被配置为接触所述腔的横向尺寸小于所述晶片直径的第二晶片表面区域，并且当所述晶片相对于所述触点移动时与所述晶片保持电接触 会员。 本发明的优点包括晶片的基本全表面处理。

公开(公告)号：US20050145484A1

公开(公告)日：2005-07-07

申请号：US11057297

申请日：2005-02-10

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: B08B1/04 ,  B24B37/04 ,  B24B53/00 ,  B24B53/007 ,  C25D5/22 ,  C25D7/12 ,  C25F3/16 ,  H01L21/288 ,  H01L21/304 ,  H01L21/768 ,  B23H7/26

CPC classification number: B24B53/017 ,  B24B37/04 ,  B24B53/001 ,  C25D5/22 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76877

Abstract: Systems and methods to remove or lessen the size of metal particles that have formed on, and to limit the rate at which metal particles form or grow on, workpiece surface influencing devices used during electrodeposition are presented. According to an exemplary method, the workpiece surface influencing device is occasionally placed in contact with a conditioning substrate coated with an inert material, and the bias applied to the electrodeposition system is reversed. According to another exemplary method, the workpiece surface influencing device is conditioned using mechanical contact members, such as brushes, and conditioning of the workpiece surface influencing device occurs, for example, through physical brushing of the workpiece surface influencing device with the brushes. According to a further exemplary method, the workpiece surface influencing device is rotated in different direction during electrodeposition.

Abstract translation: 提出了用于去除或减小在电沉积期间使用的工件表面影响装置上形成金属颗粒的尺寸并限制金属颗粒形成或生长的速率的系统和方法。 根据示例性的方法，工件表面影响装置偶尔地与涂覆有惰性材料的调理基板接触，并且施加到电沉积系统的偏压被反转。 根据另一示例性方法，使用诸如刷子的机械接触构件对工件表面影响装置进行调节，并且例如通过用刷子物理刷刷工件表面影响装置来发生工件表面影响装置的调节。 根据另一示例性方法，在电沉积期间，工件表面影响装置在不同方向上旋转。

公开(公告)号：US20050042873A1

公开(公告)日：2005-02-24

申请号：US10925358

申请日：2004-08-23

Applicant: Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

Inventor： Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

IPC: C25F3/14 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532 ,  H01L27/10 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76843 ,  C25F3/14 ,  H01L21/288 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods to operate upon a nonplanar top surface of a conductive surface layer of a workpiece, so as to, for example, preserve the structural integrity of a dielectric film layer disposed below the conductive surface layer, are presented. According to an exemplary method, a layer of conducting material such as a conducting paste is applied over the nonplanar top surface of the conductive surface layer to obtain a planar top surface. At least a portion of the conducting material layer and at least a portion of the conductive surface layer are removed in a planar manner to at least partially planarize the nonplanar top surface. The conducting material layer may be annealed so that the conducting material layer diffuses with the conductive surface layer prior to removal of at least the portions of conducting material layer and the conductive surface layer.

Abstract translation: 提供了在工件的导电表面层的非平面顶表面上操作以便例如保持设置在导电表面层下方的电介质膜层的结构完整性的系统和方法。 根据示例性方法，在导电表面层的非平面顶表面上施加诸如导电浆料的导电材料层以获得平坦的顶表面。 导电材料层的至少一部分和导电表面层的至少一部分以平面方式去除，以至少部分平坦化非平面顶表面。 导电材料层可以退火，使得在去除至少导电材料层和导电表面层的部分之前，导电材料层与导电表面层扩散。

公开(公告)号：US06612915B1

公开(公告)日：2003-09-02

申请号：US09472523

申请日：1999-12-27

Applicant: Cyprian Uzoh ,  Boguslaw Andrzej Nagorski ,  Konstantin Volodarsky ,  Douglas W. Young

Inventor： Cyprian Uzoh ,  Boguslaw Andrzej Nagorski ,  Konstantin Volodarsky ,  Douglas W. Young

IPC: B24B700

CPC classification number: B24B37/30 ,  C25D7/12

Abstract: A work piece carrier head can carry a semiconductor wafer during both plating and polishing operations. The carrier head includes a first component secured to a shaft by which the carrier head can be rotated, translated, and moved up and down, a second component connected to the first component and movable by fluid pressure relative to the first component between retracted and extended positions, and a third component connected to the first and second components for up and down movement between wafer loading or unloading and wafer plating or polishing positions. The third carrier head component includes a contact element by which electrical contact with the wafer is provided to permit wafer plating.

Abstract translation: 工件载体头可以在电镀和抛光操作期间承载半导体晶片。 承载头包括固定到轴的第一部件，承载头可以通过该第一部件旋转，平移和上下移动;第二部件，连接到第一部件并且可相对于第一部件在流体压力下相对于第一部件在缩回和延伸之间移动 位置，以及连接到第一和第二部件的第三部件，用于晶片装载或卸载以及晶片电镀或抛光位置之间的上下移动。 第三载体头部件包括接触元件，通过该接触元件提供与晶片的电接触以允许晶片电镀。

公开(公告)号：US06413403B1

公开(公告)日：2002-07-02

申请号：US09621969

申请日：2000-07-21

Applicant: Paul Lindquist ,  Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Paul Lindquist ,  Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: C25D500

CPC classification number: B24B37/26 ,  B23H5/08 ,  C25D17/001 ,  C25D17/14

Abstract: An apparatus capable of assisting in controlling an electrolyte flow and distribution of an electric field, a magnetic field, or an electromagnetic field in order to process a substrate is provided with improved fluid distribution. A support member having a top surface and a bottom surface contains at least one support member electrolyte channel. Each support member electrolyte channel forms a passage between the top surface and the bottom surface and allows the electrolyte to flow therethrough. A pad is attachable to the support member and contains at least one set of pad electrolyte channels also allowing for electrolyte flow therethrough to the substrate. Each support member electrolyte channel is connected to one set of pad electrolyte channels by fluid distribution structure. A method of assisting in control of the electrolyte flow and distribution of the electric field, the magnetic field, or the electromagnetic field, utilizing the apparatus, is also provided.

Abstract translation: 能够有助于控制电解质流动和电场分布，磁场或电磁场以便处理衬底的装置提供改进的流体分布。 具有顶表面和底表面的支撑构件包含至少一个支撑构件电解质通道。 每个支撑构件电解质通道在顶表面和底表面之间形成通道，并允许电解质流过其中。 衬垫可附接到支撑构件并且包含至少一组衬垫电解质通道，还允许电解质流过衬底。 每个支撑构件电解质通道通过流体分配结构连接到一组垫片电解质通道。 还提供了一种利用该装置协助控制电解质流动和分布电场，磁场或电磁场的方法。

公开(公告)号：US08975751B2

公开(公告)日：2015-03-10

申请号：US13092495

申请日：2011-04-22

Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia

Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia

IPC: H01L23/52 ,  H01L21/768 ,  H01L21/48 ,  H01L23/14 ,  H01L23/15 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L21/76877 ,  H01L21/486 ,  H01L21/76837 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.

Abstract translation: 微电子单元可以包括其中具有前表面和后表面的基板和其中的有源半导体器件，所述基板具有布置成在后表面的区域上的对称或不对称分布的多个开口，连接到第一和第二导电通孔的第一和第二导电通孔 在前表面暴露的焊盘，在相应的一个开口内延伸的多个第一和第二导电互连，以及暴露以与外部元件互连的第一和第二导电触点。 多个第一导电互连可以通过所述多个开口中的至少一个与所述多个第二导电互连部分开，所述至少一个开口至少部分地填充有绝缘材料。 开口的分布可以包括在第一方向上间隔开的至少m个开口和在横向于第一方向的第二方向上间隔开的n个开口。

公开(公告)号：US20120267789A1

公开(公告)日：2012-10-25

申请号：US13092495

申请日：2011-04-22

Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia

Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L21/76877 ,  H01L21/486 ,  H01L21/76837 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.

Abstract translation: 微电子单元可以包括其中具有前表面和后表面的基板和其中的有源半导体器件，所述基板具有布置成在后表面的区域上的对称或不对称分布的多个开口，连接到第一和第二导电通孔的第一和第二导电通孔 在前表面暴露的焊盘，在相应的一个开口内延伸的多个第一和第二导电互连，以及暴露以与外部元件互连的第一和第二导电触点。 多个第一导电互连可以通过所述多个开口中的至少一个与所述多个第二导电互连部分开，所述至少一个开口至少部分地填充有绝缘材料。 开口的分布可以包括在第一方向上间隔开的至少m个开口和在横向于第一方向的第二方向上间隔开的n个开口。