BACKWARD COMPATIBILITY FOR PLUG AND PLAY SYSTEMS
    51.
    发明申请
    BACKWARD COMPATIBILITY FOR PLUG AND PLAY SYSTEMS 审中-公开
    插拔和播放系统的后向兼容性

    公开(公告)号:WO1996021899A1

    公开(公告)日:1996-07-18

    申请号:PCT/US1996000014

    申请日:1996-01-11

    CPC classification number: G06F9/4411 G06F12/0646

    Abstract: A device for use in a computer system, which provides compatibility for a proposed ISA plug and play (PNP) standard. The device is also backward compatible with non-PNP (legacy) PCs. Upon power-up, a device may initialize using default traditional or specification (ISA) values for I/O address, IRQ and DMA channels. If PNP activity by the host PC is detected by the device, the device is disabled, and awaits activation and I/O address, IRQ and DMA channel assignments from a host PC. If no PNP activity by a host PC is detected, the device continues to operate using default traditional or specification (ISA) I/O address, IRQ and DMA channels. The device of the present invention may be installed in PNP or legacy type PCs without reconfiguring hardware (e.g., DIP switches, jumpers or the like) in the device or installing new firmware, operating system, or applications software in a host PC.

    Abstract translation: 一种用于计算机系统的设备,其为所提出的ISA即插即用(PNP)标准提供兼容性。 该器件也向后兼容非PNP(传统)PC。 上电时,设备可以使用I / O地址,IRQ和DMA通道的默认传统或规范(ISA)值进行初始化。 如果设备检测到主机PC的PNP活动,则该设备被禁用,并且等待主机PC的激活和I / O地址,IRQ和DMA通道分配。 如果没有检测到主机PC的PNP活动,设备将使用默认的传统或规范(ISA)I / O地址,IRQ和DMA通道继续运​​行。 本发明的设备可以安装在PNP或传统型PC中,而不重新配置设备中的硬件(例如,DIP开关,跳线等)或在主机PC中安装新的固件,操作系统或应用软件。

    METHOD AND APPARATUS FOR AUTOMATIC SECTOR PULSE GENERATION AND SPLIT FIELD CALCULATION IN DISK DRIVES
    54.
    发明申请
    METHOD AND APPARATUS FOR AUTOMATIC SECTOR PULSE GENERATION AND SPLIT FIELD CALCULATION IN DISK DRIVES 审中-公开
    磁盘驱动器自动脉冲发生和分割现场计算的方法与装置

    公开(公告)号:WO1995024036A1

    公开(公告)日:1995-09-08

    申请号:PCT/US1995002610

    申请日:1995-03-03

    Abstract: A method and apparatus for automatic sector pulse generation and split field calculation in disk drives without the use of tables improves the seek latency of a disk drive system because it does not have to wait for the INDEX mark or the beginning of a frame, before beginning an operation it has been instructed to perform. The system can be designed to start from any point on the disk and begin calculations as if it were starting from the INDEX mark or the beginning of a frame. The calculations performed for each servo mark calculate the number of sectors and split fields which can be stored between servo marks on the disk. Multiple calculations can be performed between to servo marks. A counter is used to keep track of the number of servo marks for which the system has performed calculations. This counter is compared to the number of the last previously detected servo mark. The system continues to perform the calculations for each servo mark until the counter is equal to the number of the previously passed servo mark. At this point the system is synchronized and can perform the operation that it was instructed to perform, either format, read or write. The system can also be instructed to wait for the INDEX mark or the beginning of the next frame if the system is not compatible with the fast forward method.

    Abstract translation: 在不使用表格的情况下,在磁盘驱动器中自动扇区脉冲生成和分割场计算的方法和装置改善了磁盘驱动器系统的寻道延迟,因为在开始之前不必等待INDEX标记或帧的开始 已经指示执行的操作。 该系统可以设计为从磁盘上的任何点开始,并开始计算,就像它是从INDEX标记或帧的开始开始的。 对每个伺服标记执行的计算计算可以存储在磁盘上的伺服标记之间的扇区数和分割字段数。 可以在伺服标记之间进行多次计算。 计数器用于跟踪系统执行计算的伺服标记的数量。 该计数器与最后检测到的伺服标记的数量进行比较。 系统继续执行每个伺服标记的计算,直到计数器等于先前通过的伺服标记的数量。 在这一点上,系统是同步的,可以执行它被指示执行的格式,读取或写入操作。 如果系统与快进方法不兼容,还可以指示系统等待INDEX标记或下一帧的开始。

    BURST ERROR CORRECTOR
    55.
    发明申请

    公开(公告)号:WO1995012849A1

    公开(公告)日:1995-05-11

    申请号:PCT/US1994012134

    申请日:1994-10-18

    Abstract: A burst error correction system which comprises a CRC generator/checker (20); a syndrome/ECC generator (30) and an error corrector (40). Using codeword data, the CRC generator/checker (20) generates m number of CRC bytes. The CRC bytes are shifted out to the syndrome/ECC generator (30) for use in the generation of a plurality of ECC bytes. The ECC bytes are generated so that the sum of the bytes in each interleave for a codeword is zero, and that the ECC bytes generated by the syndrome/ECC generator (30) constitutes at least L number of consecutive roots of the codeword.

    Abstract translation: 一种突发纠错系统,包括CRC发生器/检验器(20); 综合征/ ECC发生器(30)和误差校正器(40)。 使用码字数据,CRC生成器/检查器(20)生成m个CRC字节。 CRC字节被移出到校正子/ ECC生成器(30),用于生成多个ECC字节。 生成ECC字节,使得码字的每个交织中的字节的和为零,并且由校验子/ ECC生成器(30)生成的ECC字节构成码字的至少L个连续的根。

    PROGRAMMABLE REDUNDANCY/SYNDROME GENERATOR
    56.
    发明申请
    PROGRAMMABLE REDUNDANCY/SYNDROME GENERATOR 审中-公开
    可编程冗余/综合发电机

    公开(公告)号:WO1995008803A2

    公开(公告)日:1995-03-30

    申请号:PCT/US1994010668

    申请日:1994-09-20

    CPC classification number: G06F11/1004 G06F11/10 H03M13/151

    Abstract: A hardware implementation of an error correcting encoder/decoder for polynomial codes which uses a single circuit to generate check symbols during the transmit operation and generate syndromes during a receive operation is disclosed. The selection of roots for the code generator and hence the code order is programmable.

    Abstract translation: 公开了一种用于多项式代码的纠错编码器/解码器的硬件实现,其使用单个电路在发送操作期间产生校验符号并且在接收操作期间产生校正符号。 代码生成器的根的选择以及代码顺序是可编程的。

    FLASHMEMORY MASS STORAGE ARCHITECTURE
    57.
    发明申请
    FLASHMEMORY MASS STORAGE ARCHITECTURE 审中-公开
    闪存大容量存储架构

    公开(公告)号:WO1994023432A1

    公开(公告)日:1994-10-13

    申请号:PCT/US1994003154

    申请日:1994-03-23

    Abstract: A semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. (The erase cycle is understood to include, fully programming the block to be erased, and then erasing the block.) Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, means are provided for evenly using all blocks in the mass storage. These advantages are achieved through the use of several flags, a map (108) to correlate a logical address (308) of a block to a physical address (408) of that block and a count register for each block. In particular, flags (118, 112, 116) are provided for defective blocks, used blocks, old version of a block, and a count to determine the number of times a block has been erased and written and erase inhibit flag.

    Abstract translation: 半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时,系统和架构避免了擦除周期。 (擦除周期被理解为包括完全编程要擦除的块,然后擦除块)。通过将更改后的数据文件编程为空的大容量存储块而不是将硬盘自身编程,可以避免擦除周期。 定期地,大容量存储将需要清理。 其次,提供均匀地使用大容量存储器中的所有块的装置。 这些优点通过使用几个标志来实现,地图(108)将块的逻辑地址(308)与该块的物理地址(408)和每个块的计数寄存器相关联。 特别地,为缺陷块,使用块,块的旧版本以及用于确定块被擦除的次数和写入和擦除禁止标志的计数提供标志(118,112,116)。

    DIGITAL PULSE DETECTOR
    58.
    发明申请
    DIGITAL PULSE DETECTOR 审中-公开
    数字脉冲检测器

    公开(公告)号:WO1993023941A1

    公开(公告)日:1993-11-25

    申请号:PCT/US1993004234

    申请日:1993-05-05

    CPC classification number: G11B20/10037 G11B20/10009 G11B20/1403 H03K5/19

    Abstract: Disclosed is a pulse detector (312) that uses four samples (406, 408, 410, 412, 504, 506, 508, 510) of an analog signal to detect a pulse as soon as one sample beyond the time of the peak of signal level at the pulse. The pulse detector can detect pulses by sampling at the center of a peak of the pulse or by sampling at either side of the peak of the pulse. The pulse detector detects pulses while tracking data, and it uses an alternate detection system for detecting pulses while acquiring timing and gain lock on a signal having a known data pattern. The detector uses either the sampled signal levels directly, or a moving average of two samples to perform the detection.

    Abstract translation: 公开了一种脉冲检测器(312),其使用模拟信号的四个采样(406,408,410,412,504,508,508,510)来检测脉冲,一旦超过信号峰值时间的一个采样 脉冲电平。 脉冲检测器可以通过在脉冲峰值的中心采样或通过在脉冲峰值的任一侧进行采样来检测脉冲。 脉冲检测器在跟踪数据的同时检测脉冲,并且在采集具有已知数据模式的信号的定时和增益锁定的同时使用备用检测系统来检测脉冲。 检测器使用采样信号电平或两个采样的移动平均值进行检测。

    PROCESS FOR PRODUCING SHADED COLOR IMAGES ON DISPLAY SCREENS
    59.
    发明申请
    PROCESS FOR PRODUCING SHADED COLOR IMAGES ON DISPLAY SCREENS 审中-公开
    在显示屏幕上生成阴影彩色图像的过程

    公开(公告)号:WO1993020549A1

    公开(公告)日:1993-10-14

    申请号:PCT/US1993003326

    申请日:1993-04-07

    CPC classification number: G09G3/3607 G09G3/2018 G09G3/2025 G09G3/2051

    Abstract: A process for producing a wide range of colors in images that are presented in successive frames on image fields (13) on color opto-electronic display means having separate illumination elements each of a different color at each pixel location. Each pixel location, for example, may have a red, a green and a blue illumination element. The display is divided into uniformly-sized display neighborhoods (17). The process includes, for a given pixel location (a-p) within any one of the uniformly-sized display neighborhoods, producing a given color at that pixel location by selecting a frame sequence for illuminating the illumination elements at the pixel location during presentation of an image wherein the number of times that any given illumination element at the pixel location is illuminated within a given frame sequence is controlled to create an appearance of color shading of that pixel location relative to other pixel locations and wherein adjacent pixel locations that have the same color within any one of the display neighborhoods have their illumination elements illuminated with different frame sequences to minimize display noise.

    Abstract translation: 在彩色光电显示装置上的图像场(13)上的连续帧中呈现的图像中的宽范围的颜色的处理,其具有在每个像素位置处具有不同颜色的分离的照明元件。 例如,每个像素位置可以具有红色,绿色和蓝色照明元件。 显示器被分成均匀尺寸的显示区域(17)。 该过程包括对于在均匀尺寸的显示器邻域中的任何一个中的给定像素位置(ap),通过在呈现图像期间选择用于照亮像素位置处的照明元素的帧序列来产生该像素位置处的给定颜色 其中控制像素位置处的任何给定的照明元件在给定的帧序列内照亮的次数,以产生该像素位置相对于其它像素位置的色彩的外观,并且其中具有相同颜色的相邻像素位置 显示区域中的任何一个具有以不同帧序列照亮的照明元件,以最小化显示噪声。

    METHOD AND DEVICE FOR DEBUGGER AND TEST DATA COLLECTOR
    60.
    发明申请
    METHOD AND DEVICE FOR DEBUGGER AND TEST DATA COLLECTOR 审中-公开
    调试器和测试数据收集器的方法和设备

    公开(公告)号:WO1998057486A1

    公开(公告)日:1998-12-17

    申请号:PCT/US1998011620

    申请日:1998-06-10

    CPC classification number: H04L43/50 G06F19/00

    Abstract: A computer system comprises a plurality of user computers interconnected through a public-switched telephone network and trunk lines, and also includes a plurality of Remote Data Processing Nodes (RDPNs) similarly connected to each other and to the user computers. A BBS station which is also coupled to the network receives test data from the user computers. Each user computer includes a test unit that includes a digital signal processor and an active control unit. The test unit has a dialing directory for connecting to various BBSs to test out the communication through a modem and the telephone network. Using the dialing directory, the test unit activates the modem to make a predetermined call through the telephone network to several of the RDPNs. The test unit collects survey, snapshot and real-time data packets in a predetermined data file which are communicated to the BBS station for debugging the system and determining the performance of the system.

    Abstract translation: 计算机系统包括通过公共交换电话网和中继线互连的多个用户计算机,并且还包括彼此类似地连接到用户计算机的多个远程数据处理节点(RDPN)。 也耦合到网络的BBS站从用户计算机接收测试数据。 每个用户计算机包括测试单元,其包括数字信号处理器和主动控制单元。 测试单元具有用于连接到各种BBS的拨号目录,以通过调制解调器和电话网络测试通信。 使用拨号目录,测试单元激活调制解调器,通过电话网络进行预定的呼叫到几个RDPN。 测试单元在预定的数据文件中收集调查,快照和实时数据分组,该预定数据文件被传送到BBS站以调试系统并确定系统的性能。

Patent Agency Ranking