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公开(公告)号：JPH10163755A
公开(公告)日：1998-06-19
申请号：JP31653796
申请日：1996-11-27
Applicant: FUJITSU LTD
Inventor： YAMAMOTO AKIRA , TAJIMA MASAYA , UEDA TOSHIO , KURIYAMA HIROHITO , ISHIDA KATSUHIRO , KANAZAWA GIICHI
IPC: G09F9/313 , G09G3/20 , G09G3/288 , G09G3/291 , G09G3/296 , G09G3/298 , G09G5/20 , H03B28/00 , G09G3/28
Abstract: PROBLEM TO BE SOLVED: To provide a waveform generating circuit with which the amount of ROM data can be reduced and complicated waveforms can be generated. SOLUTION: This waveform generating circuit is provided with a ROM 651 storing waveforms and waveform data concerning its generation for each cycle, address generating circuit 71 for successively generating address signals for successively reading the waveform data, and waveform data output circuit 73 for successively reproducing the read waveform data in waveform signals. In this case, the waveform data contains extension information instructing the extended reproduction of waveform data in that cycle and an extension discrimination/control circuit 72 is provided for discriminating the presence/ absence of extension information from the read waveform data, performing control to maintain the output of correspondent waveform signal at a waveform data output circuit when the extension information is contained, and performing control so as to delay the generating operation of address signals at the address generating circuit.
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公开(公告)号：JPH09127911A
公开(公告)日：1997-05-16
申请号：JP28297395
申请日：1995-10-31
Applicant: FUJITSU LTD
Inventor： TAJIMA MASAYA , UEDA TOSHIO , KURIYAMA HIROHITO , ISHIDA KATSUHIRO , YAMAMOTO AKIRA
Abstract: PROBLEM TO BE SOLVED: To flexibly cope with the high vertical synchronization frequency resulting from a multi-scan by selecting the number of display-controllable subframes in response to the frequency of the inputted vertical synchronization signal, and controlling the display in response to the selected subframe number. SOLUTION: A clock VC indicating the start of a frame is generated from the vertical synchronization signal Vsync. When the clock VC is applied to a subframe counter 52 as the load pulse, the subframe set value is loaded into a subframe counter 52 from a subframe number set ROM 51. The subframe counter 52 outputs the count value corresponding to the selected subframe number thereafter. The inputted display data are converted into the display data having the bit number corresponding to the subframe number, alignment- converted into the address data for each line, and written in a frame memory by the pseudo gradation process section of a display data controller.
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公开(公告)号：JP2552005B2
公开(公告)日：1996-11-06
申请号：JP25586589
申请日：1989-09-29
Applicant: FUJITSU LTD
Inventor： UEDA TOSHIO
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公开(公告)号：JPH07261699A
公开(公告)日：1995-10-13
申请号：JP1533195
申请日：1995-02-01
Applicant: FUJITSU LTD
Inventor： YAMAMOTO AKIRA , OTSUKA AKIRA , UEDA TOSHIO , KANAZAWA GIICHI , TOMIO SHIGETOSHI
Abstract: PURPOSE:To provide a planar display device such as a plasma display, etc., reducing power consumption in a maintenance discharge period at the time of interlace display operation. CONSTITUTION:This device is the planar display device dividing a Y side electrode group 15 constituting one field displaying one picture into a first set consisting of odd lines and a second set consisting of even lines, controlling so that respective sets of the Y side electrode group 15 form a first sub-field and a second sub-field respectively, performing the interlace display operation alternately selecting the first subfield and the second sub-field and executing the display operation at the time of the display operation and maintaining the Y side electrode 15 in the sub-field not selected in high impedance state for the maintaining discharge period.
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公开(公告)号：JPH07121120A
公开(公告)日：1995-05-12
申请号：JP26658593
申请日：1993-10-25
Applicant: FUJITSU LTD
Inventor： NAGAOKA YOSHIMASA , KANEKO KEIICHI , UEDA TOSHIO
IPC: G09G3/28 , G09F9/00 , G09G3/20 , G09G3/288 , G09G3/291 , G09G3/294 , G09G3/32 , H01J11/00 , H01J11/12 , H01J11/24
Abstract: PURPOSE:To set optimum luminance and contrast by making the plasma display panel and a back lighting body device variable in luminance. CONSTITUTION:A back lighting device 22 is arranged on the back side of be plasma display panel(PDP) 10 and then driven by a driver 24. The river 24 is controlled by the driving control circuit 26 for the back lighting device 22. There are two adjustment modes for the luminance and contrast. The 1st mode is an individual luminance adjustment mode for adjusting the luminance values of the PDP 10 and back lighting device 22 individually and the 2nd mode is a mode for adjusting the luminance values of the PDP 10 and back lighting device 22 relatively so that the contrast is held constant. Thus, the luminance of the PDP 10 and back lighting device 22 is adjusted to set the optimum luminance and contrast.
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Patent Agency Ranking
公开(公告)号：JPH0777947A
公开(公告)日：1995-03-20
申请号：JP22477493
申请日：1993-09-09
Applicant: FUJITSU LTD
Inventor： TAJIMA MASAYA , UEDA TOSHIO
Abstract: PURPOSE:To reduce or prevent the contour coloring in a moving image area even when a display signal from a source is displayed on a display device with dispersion in responsiveness according to a display color as it is by displaying the data of a later frame related to the display color with a low display responce speed. CONSTITUTION:An image display device is constituted of frame buffers Fr and Fb and the display device P1 with the low display responce speed of G (green). Related to the video signal R data of a red color and the video signal Bdaca of a blue color, they are suppimed to the display device P1 through respective frame buffers Fr and Fb, and the video signal Gdata of a green color is supplied to the display device Pi directly. Thus, the G (green) color with the low dispiay responce speed is displayed using the frame data later in proportion to the frame data of the R (red) and B (blue) supplied to the display device simultaneously.
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公开(公告)号：JPH0572993A
公开(公告)日：1993-03-26
申请号：JP23611991
申请日：1991-09-17
Applicant: FUJITSU LTD
Inventor： UEDA TOSHIO
Abstract: PURPOSE:To control a gradational display at a specific gradation ratio at all times without varying the ratio of the brightness of a screen even if the number of horizontal synchronizing signals in a one-frame period varies by setting the delay time of scanning timing following precedent scan timing according to a specific value. CONSTITUTION:When the gradational display is made on the gas discharge panel by a multiple address method, the delay time of the scan timing following the precedent scan timing is set according to the value (M) obtained by dividing the number (LN) of horizontal synchronizing signal in the one-frame period by the weighted sum of display data rewritten by precedent scanning operation and display data rewritten by following scanning operation. For the purpose, a divider 500 which inputs the value LN from a scan controller 400 and finds the value M is provided and the calculated division value is inputted as the value M to the scan controller 400.
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公开(公告)号：JPH04127194A
公开(公告)日：1992-04-28
申请号：JP24747090
申请日：1990-09-19
Applicant: FUJITSU LTD
Inventor： UEDA TOSHIO
Abstract: PURPOSE:To prevent a flicker from being generated owing to fluctuations of brightness between nearby lines by providing a means which divides a field large in time rate and separates the divided fields mutually at constant time intervals on the input side of a display period setting means. CONSTITUTION:The field dividing and separating means 4 which divides the field large in time rate and separates the divided fields mutually at the constant time intervals is provided on the input side of the display period setting means 2. Then when one frame is divided into the fields and a gradational display of data is made, the field which is large in time rate is further divided to increase the display inversion frequency in the field apparently. Consequently, even when a combination of gradations where nearby lines of a display panel are inverted in display period is obtained, a flicker is prevented from being generated at the border between those lines.
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公开(公告)号：JPH03118630A
公开(公告)日：1991-05-21
申请号：JP25586589
申请日：1989-09-29
Applicant: FUJITSU LTD
Inventor： UEDA TOSHIO
Abstract: PURPOSE:To eliminate the selection errors and the complicacy of selection by providing an automatic recognizing circuit for display data input bit number and selecting an input interface circuit based on the recognizing result of the recognizing circuit. CONSTITUTION:The display data signals DATA1, DATA2... DATAn have differ ent numbers of input bits and are corresponding in 1:1 to the input interface circuits 181, 182... 18n. Then an automatic recognizing circuit 20 for display data input bit number is provided to automatically recognize the number of input bits of the signals DATA1, DATA2... DATAn. In other words, the presently working input interface circuit is decided. Then an input interface selection circuit 19 selects the working input interface circuit based on the recognizing result of the circuit 20 and connects the selected interface circuit to an internal circuit 13. In such a constitution, the input interface circuits can be automati cally selected.
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公开(公告)号：JP2005134922A
公开(公告)日：2005-05-26
申请号：JP2004366683
申请日：2004-12-17
Applicant: Fujitsu Ltd , 富士通株式会社
Inventor： UEDA TOSHIO , ISHIDA KATSUHIRO
Abstract: PROBLEM TO BE SOLVED: To overcome problem that sections where luminescence is dense or non-dense are formed and bright or dark lines are produced, when an image with grayscale change (luminance change) in-plane is displayed by scrolling, in a conventional sub-frame type halftone display method.
SOLUTION: In an intraframe time division type display apparatus in which one frame image displayed in the display apparatus is comprised of a plurality of sub-frames and luminance is independently set for each sub-frame in the plurality of sub-frames, when predetermined grayscale change is performed, luminescence dense section 32 G, 32 B and 31 R generated by coupling sub-frames are suppressed by turning off light emission of a part of sub-frames 31 and 31 in the coupled sub-frame.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：为了克服形成致密或不密集发光的部分和产生明亮或暗线的问题，当通过滚动显示平面内灰度变化（亮度变化）的图像时，在 常规的子帧型半色调显示方法。 解决方案：在其中在显示装置中显示的一个帧图像由多个子帧组成并且对于多个子帧中的每个子帧独立设置亮度的帧内时分类型显示装置中， 当执行预定的灰度改变时，通过关闭子帧31 <1的一部分的发光来抑制通过耦合子帧产生的发光致密部分32 2 G，32 B和31 1 R 和31 <2>。 版权所有（C）2005，JPO＆NCIPI
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