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公开(公告)号：JPH0968946A
公开(公告)日：1997-03-11
申请号：JP22666795
申请日：1995-09-04
Applicant: FUJITSU LTD
Inventor： KANAZAWA GIICHI , NAGAOKA YOSHIMASA , MATSUI NAOKI , HIROSE TADATSUGU , MACHIDA ATSUSHI , GUEN TAN NIYAN
IPC: G09G3/291 , G09G3/20 , G09G3/288 , G09G3/292 , G09G3/293 , G09G3/294 , G09G3/296 , G09G3/298 , G09G3/28
Abstract: PROBLEM TO BE SOLVED: To make an address data driver low breakdown strength, to simplify a power source, to suppress the generation of a noise at the fall time of a sustaining discharge pulse and to guarantee stable sustaining discharge in a sustaining discharge period when a display device such as an AC type PDP is driven. SOLUTION: A first and a second electrodes are arranged on a first substrate, a third electrode is arranged on a second substrate opposing to the first substrate, when write-in in a display cell selected by the first or the second electrode and the third electrode is performed, this device is provided with a first voltage supplying means 4 for supplying a half voltage of a prescribed voltage necessary for the sustaining discharge to the first electrode and a second voltage supplying means 5 for supplying a half voltage of a prescribed voltage having different polarity, the potential for selecting the second electrode in an addressing period has an equivalent voltage as that in the period of sustaining discharge and the equivalent voltage as that in the period of sustaining discharge having the reversed polarity to the voltage of the second electrode is applied on the first electrode.
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公开(公告)号：JPH07121120A
公开(公告)日：1995-05-12
申请号：JP26658593
申请日：1993-10-25
Applicant: FUJITSU LTD
Inventor： NAGAOKA YOSHIMASA , KANEKO KEIICHI , UEDA TOSHIO
IPC: G09G3/28 , G09F9/00 , G09G3/20 , G09G3/288 , G09G3/291 , G09G3/294 , G09G3/32 , H01J11/00 , H01J11/12 , H01J11/24
Abstract: PURPOSE:To set optimum luminance and contrast by making the plasma display panel and a back lighting body device variable in luminance. CONSTITUTION:A back lighting device 22 is arranged on the back side of be plasma display panel(PDP) 10 and then driven by a driver 24. The river 24 is controlled by the driving control circuit 26 for the back lighting device 22. There are two adjustment modes for the luminance and contrast. The 1st mode is an individual luminance adjustment mode for adjusting the luminance values of the PDP 10 and back lighting device 22 individually and the 2nd mode is a mode for adjusting the luminance values of the PDP 10 and back lighting device 22 relatively so that the contrast is held constant. Thus, the luminance of the PDP 10 and back lighting device 22 is adjusted to set the optimum luminance and contrast.
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公开(公告)号：JP2001013910A
公开(公告)日：2001-01-19
申请号：JP18083299
申请日：1999-06-25
Applicant: FUJITSU LTD
Inventor： NAGAOKA YOSHIMASA , UCHIYAMA KOICHIRO , TAKAMORI TAKAHIRO
Abstract: PROBLEM TO BE SOLVED: To obtain a driving method, which prevents mallighting of a non- turned on cell, by providing a first discharging process that applies a specific voltage between first and second electrodes. SOLUTION: A low Vfe non-turned on cell is normally in a condition in which no wall electric charge exists because no maintaining discharge is conducted during a maintaining discharge period. However, there is a case in which slight amount of wall electric charges exists by the effect of discharges made by the turned on cells located at the top and the bottom and the right and the left of the non-turned on cell. OC pulses have a positive pulse to be applied to an X electrode and a negative pulse to be applied to a Y electrode. The applied voltages are set not to exceed a discharge starting voltage. However, the voltages are added by residual wall electric charges at the completion time of the maintaining discharge period. If the amount of finite wall electric charges is large, the potential between the electrodes exceeds as discharge starting voltage, discharges take place by the OC pulses and wall electric charges are formed. At that time, the cell has approximately the same wall electric charges of a normal turned on cell. Therefore, a complete erasing is conducted by the erasing discharge in a rest period later.
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公开(公告)号：JP2000305519A
公开(公告)日：2000-11-02
申请号：JP11377399
申请日：1999-04-21
Applicant: FUJITSU LTD
Inventor： KISHI TOMOKATSU , UCHIYAMA KOICHIRO , NAGAOKA YOSHIMASA , TAKAMORI TAKAHIRO
Abstract: PROBLEM TO BE SOLVED: To surely realize driving for lighting accurately cells to be lit and not for lighting accurately cells not to be lit, based on display data. SOLUTION: During a reset period after finish of a sustained discharge period, erasing discharges are executed respectively by applying pulse voltages having mutually different waveforms between a first erasing discharge period having, as an object, lighting cells which were lit during the preceding sustained discharge period and a second erasing discharge period having, as an object, not only lighting cells but also non-lighting cells which were not lit during the preceding sustained discharge period. Hereby, a feeble wall charge which was not completely erased during the first erasing discharge period, namely, the feeble wall charge accumulated on the non-lighting cells by being influenced by the lighting cells, can be erased during the second erasing discharge period. Therefore, the non-lighting cells which are not to be lit essentially are prevented from being lit during the next address period and sustained discharge period, to improve a driving voltage margin.
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公开(公告)号：JPH11133913A
公开(公告)日：1999-05-21
申请号：JP19601698
申请日：1998-07-10
Applicant: FUJITSU LTD
Inventor： NAGAOKA YOSHIMASA , TAKAMORI TAKAHIRO , TOMIO SHIGETOSHI , HIROSE TADATSUGU , KANEKO KEIICHI , KAMEYAMA SHIGEKI , KISHI TOMOKATSU , SAKAMOTO TETSUYA , TAKAGI AKIHIRO
Abstract: PROBLEM TO BE SOLVED: To improve the driving voltage margin at the time of driving a plasma display panel by applying the narrow width pulse as an eliminating pulse for eliminating the only cell lighted in the last sub field for elimination discharge. SOLUTION: Full surface writing discharge is not performed in a sub field sFn+1, and the elimination pulse of the narrow width pulse having 2 μs or less of pulse width is applied to an X electrode so as to eliminate a wall charge. The narrow width pulse concludes the apply of the pulse voltage immediately after forming discharge, and almost of the charged particles generated at the time of discharge are left in a discharging cell space, and attracted to the wall charge on a panel dielectric layer by the electrostatic force, and connected again on the wall surface so as to be eliminated. Opposite electrode electrical potential during the maintenance discharge period of a three-electrode structure panel is set at an intermediate value of an electrical potential between the maintenance discharge electrodes so as to stabilize the operation of the panel. With this structure, even at the time of discharge for eliminating the narrow width pulse having a pulse width at 2 μs or less, the opposite electrode is maintained at a positive electrode electrical potential during the maintenance discharge period.
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Patent Agency Ranking
公开(公告)号：JPH0744127A
公开(公告)日：1995-02-14
申请号：JP19070093
申请日：1993-08-02
Applicant: FUJITSU LTD
Inventor： NAGAOKA YOSHIMASA , KANAZAWA GIICHI , KISHI TOMOKATSU
Abstract: PURPOSE:To obtain accurate display gradations and to improve the display quality of a gradation display by varying the level of maintaining pulses according to a display rate. CONSTITUTION:The value from a high voltage generating circuit 30 to a high voltage control circuit part 29 is different between an address period and a trickle discharge period. An external high voltage VS is supplied as it is in the address period, but in the trickle discharge period, a variable high voltage VS+alpha which is adjusted according to the current display rate of the display data is supplied. Therefore, the level of the maintaining pulses VS in the trickle discharge period varies with the display rate. Further, the luminance of a screen varies in proportion to the level of the maintaining pulses VS, so the level of the adjusting voltage alpha (data stored in a data converting ROM 32) is optimized to display a high-gradation display part and a low-gradation display part with correct lightness even in case of, for example, a 256-gradation or more gradation display.
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公开(公告)号：JP2000089720A
公开(公告)日：2000-03-31
申请号：JP25682598
申请日：1998-09-10
Applicant: FUJITSU LTD
Inventor： SAKAMOTO TETSUYA , KISHI TOMOKATSU , TOMIO SHIGETOSHI , NAGAOKA YOSHIMASA , TAKAMORI TAKAHIRO , MACHIDA ATSUSHI , TAKAGI AKIHIRO
Abstract: PROBLEM TO BE SOLVED: To realize a driving method of PDP in which background light by light emission of a whole cell is reduced and contrast and linearity of gradation display are improved. SOLUTION: This method is a driving method of PDP provided with first and second electrodes 12, 11, and plural third electrode 13 arranged in a form of intersecting at right angle to plural pairs of the first and the second electrodes. Further the method is provided with a reset process in which self erasion discharge is performed in plural cells 10 by applying reset voltage, an address process in which electric charges corresponding to display data are accumulated for each cell, and a maintaining discharge process in which maintaining discharge voltage is applied to plural cells and discharge is caused by cells accumulated with the prescribed electric charges an light emission is performed. In this case, reset voltage is set so that self erasion discharge is caused when reset voltage is superimposed on electric charges accumulated in electrodes of plural cells, self erasion discharge is caused selectively in a part of plural cells.
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公开(公告)号：JPH10143108A
公开(公告)日：1998-05-29
申请号：JP30070196
申请日：1996-11-12
Applicant: FUJITSU LTD
Inventor： KANAZAWA GIICHI , NAGAOKA YOSHIMASA
Abstract: PROBLEM TO BE SOLVED: To prevent residual charges from being generated and to enable stable address discharging without causing any increase in power consumption by making the potential difference between electrodes at the time of reset discharging opposite in polarity from the potential difference between the electrodes at the time of selective discharging by the electrodes in an address period. SOLUTION: In an entire-surface writing process, a voltage of, for example, -120V is applied to a maintenance electrode X1 and a voltage of 180V is applied to a scanning electrode Y1 . Consequently, wall charges are generated on the respective electrodes. Then the voltages in the entire-surface writing process are made opposite in application polarity. Consequently, the wall surfaces accumulated on the maintenance electrodes X1 and scanning electrode Y1 are opposite in polarity from each other. In an address process, remaining wall charges having such a polarity that they are added to an address voltage applied between electrodes A1 and Y1 . Therefore, the voltage applied between the electrodes A1 and Y1 is never lowered under the influence of the residual charges and the address discharging can stably be performed.
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公开(公告)号：JPH09179520A
公开(公告)日：1997-07-11
申请号：JP33695195
申请日：1995-12-25
Applicant: FUJITSU LTD
Inventor： NAGAOKA YOSHIMASA , KARIYA NORIJI , MATSUI NAOKI , KANAZAWA GIICHI
Abstract: PROBLEM TO BE SOLVED: To realize a PDP(plasma display panel) driving method of more surely lighting a cell to be lighted and a PD device reducing such defect that the cell to the lighted has defective flicker. SOLUTION: This device is provided with the plasma display panel 100, a scan driver 102 successively scanning and applying a scan pulse to plural scan lines, an address driver 105 applying a voltage answering to the display data to plural address lines by one line in the period that respective scan pulses are applied and support discharge means 103, 104 applying a support discharge voltage to plural cells, causing a discharge of the cell storing a prescribed charge and emitting light. In such a case, the device is provided with a control means 106 controlling the scan driver 102 so as to apply a long scan pulse to the scan line such as a first line containing many cells having high address discharge defect probability.
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公开(公告)号：JPH096283A
公开(公告)日：1997-01-10
申请号：JP15060895
申请日：1995-06-16
Applicant: FUJITSU LTD
Inventor： NAGAOKA YOSHIMASA , MATSUI NAOKI , KANAZAWA GIICHI
Abstract: PURPOSE: To provide a temperature compensating method and heating preventing method for plasma display panel(PDP), which compensates the temperature so as not to affect on the display characteristic of the PDP even when the temperature is raised by driving, and is capable of protecting a plasma display device containing the PDP from the temperature rising. CONSTITUTION: The temperature compensating device of a PDP 1 detects the temperature of the PDP 1 and the temperature of drives 5, 7, and corrects the luminance of the PDP 1 based on the detected values. In this case, the number of maintaining discharge pulses is controlled and corrected, and maintaining discharge voltage is also controlled and corrected. In addition, the gradation value of display data DATA is controlled. In the heating preventing device of the PDP 1, the whole device is cooled by an air cooling device 80 based on each temperature, and a warning is sent out to a user with an LED 70. Furthermore, the power source is shut off with a relay control part 91.
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