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    51.
    发明专利
    未知

    公开(公告)号：DE69118584T2

    公开(公告)日：1996-10-24

    申请号：DE69118584

    申请日：1991-05-09

    Applicant: IBM

    Inventor： PATEL ARVIND MOTIBHAI ,  RUTLEDGE ROBERT ANTHONY

    IPC: H03M7/46 ,  G11B20/10 ,  G11B20/14 ,  H03M5/14 ,  H03M7/14 ,  H04L25/49

    Abstract: A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved. A phase check is not necessary.

    53.
    发明专利
    未知

    公开(公告)号：DE69118584D1

    公开(公告)日：1996-05-15

    申请号：DE69118584

    申请日：1991-05-09

    Applicant: IBM

    Inventor： PATEL ARVIND MOTIBHAI ,  RUTLEDGE ROBERT ANTHONY

    IPC: H03M7/46 ,  G11B20/10 ,  G11B20/14 ,  H03M5/14 ,  H03M7/14 ,  H04L25/49

    Abstract: A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved. A phase check is not necessary.

    54.
    发明专利
    未知

    公开(公告)号：DE68920523T2

    公开(公告)日：1995-07-20

    申请号：DE68920523

    申请日：1989-08-24

    Applicant: IBM

    Inventor： EGGENBERGER JOHN SCOTT ,  HODGES PAUL ,  PATEL ARVIND MOTIBHAI

    IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00

    Abstract: A method is disclosed for correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise sub-blocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading. A sequence of N sequential parity check bytes is written at the end of each block. After ECC syndromes are generated during reading, parity syndromes are generated by comparing parity check bytes computed from data bytes and check bytes as read with the parity check bytes as written. When a long-burst error occurs, a pointer points to the first of the N consecutive bytes in a block that could have been influenced by the error burst. After correcting correctable errors in all sub-blocks not affected by the N bytes identified by the pointer, and adjusting the parity syndromes for errors thus corrected, the adjusted parity syndromes are used to correct the errors in the N bytes indicated by the pointer. Unused ECC syndromes are then adjusted for errors corrected by the adjusted parity syndromes and used to correct all correctable errors then remaining.

    57.
    发明专利
    未知

    公开(公告)号：DE3787900T2

    公开(公告)日：1994-05-05

    申请号：DE3787900

    申请日：1987-02-10

    Applicant: IBM

    Inventor： PATEL ARVIND MOTIBHAI

    IPC: H03M13/00 ,  G11B20/18 ,  H03M13/09

    Abstract: The present invention relates to apparatus for generating a set of CRC check bytes for a variable-length record formed as a sequence of data bytes and error correction check bytes inserted into the sequence of data bytes at preselected intervals. The apparatus comprises a computing system adapted to operate on the sequence of data bytes and error correction check bytes in order to generate the set of CRC check bytes. … According to the invention the apparatus is characterised in that the computing system comprises… first computing means for sequentially receiving the sequence of data bytes and error correction check bytes in the record and for multiplying all the data bytes and error correction check bytes, except for a first preselected set of the error correction check bytes, by a matrix of the form T , where n is an integer and different from any integer used for computing the error correction check bytes, in order to generate a first sub-set of CRC check bytes,… second computing means for sequentially receiving the sequence of data bytes and error correction check bytes in the record and for multiplying all the data bytes and error correction check bytes, except for a second preselected set of the error correction check bytes, by a matrix of the form T in order to generate a second sub-set of CRC check bytes, and… means for combining the first and second sub-sets of CRC check bytes so as to generate the set of CRC check bytes.

    METHOD AND SYSTEM FOR CORRECTING LONG BURSTS OF CONSECUTIVE ERRORS
    60.
    发明专利
    METHOD AND SYSTEM FOR CORRECTING LONG BURSTS OF CONSECUTIVE ERRORS 未知

    公开(公告)号：AU616788B2

    公开(公告)日：1991-11-07

    申请号：AU3928289

    申请日：1989-08-03

    Applicant: IBM

    Inventor： PATEL ARVIND MOTIBHAI ,  HODGES PAUL ,  EGGENBERGER JOHN SCOTT

    IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00

    Abstract: A method is disclosed for correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise sub-blocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading. A sequence of N sequential parity check bytes is written at the end of each block. After ECC syndromes are generated during reading, parity syndromes are generated by comparing parity check bytes computed from data bytes and check bytes as read with the parity check bytes as written. When a long-burst error occurs, a pointer points to the first of the N consecutive bytes in a block that could have been influenced by the error burst. After correcting correctable errors in all sub-blocks not affected by the N bytes identified by the pointer, and adjusting the parity syndromes for errors thus corrected, the adjusted parity syndromes are used to correct the errors in the N bytes indicated by the pointer. Unused ECC syndromes are then adjusted for errors corrected by the adjusted parity syndromes and used to correct all correctable errors then remaining.

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