-
公开(公告)号：JP2003015825A
公开(公告)日：2003-01-17
申请号：JP2002136492
申请日：2002-05-13
Inventor： HODGES PAUL , HURLEY MICHAEL GARWOOD , OUCHI NORMAN KENNETH , SHIH MIEN
CPC classification number: G06F13/1642
Abstract: PROBLEM TO BE SOLVED: To provide a high performance storage subsystem with a plurality of independent paths for communication between a storage controller and a storage device.
SOLUTION: This data processing system has a plurality of independent paths 352, 354 for the communication between a host and a plurality of storage devices. Each path has its own queue 413, 415, services a requests generated by the host and accesses the storage devices 345. Each request is assigned a unique sequential ID and after that, stored in all the queues along with the ID, Each storage device has a 'mailbox' register 500 to store the ID and a status of the executed latest ID. Queues are serviced and their status are updated based on the contents of the mailbox. Consequently, the queue in each path is allowed to be completely out of synchronization with each queue in other paths.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：提供具有用于存储控制器和存储设备之间的通信的多个独立路径的高性能存储子系统。 解决方案：该数据处理系统具有用于主机和多个存储设备之间的通信的多个独立路径352,354。 每个路径具有自己的队列413,415，服务于由主机产生的请求并访问存储设备345.每个请求被分配唯一的顺序ID，之后与所有ID一起存储在所有队列中，每个存储设备具有 用于存储ID和所执行的最新ID的状态的“邮箱”寄存器500。 服务队列并根据邮箱的内容更新其状态。 因此，允许每个路径中的队列与其他路径中的每个队列完全不同步。
-
公开(公告)号：DE2508706A1
公开(公告)日：1975-11-20
申请号：DE2508706
申请日：1975-02-28
Applicant: IBM
Inventor： EGGENBERGER JOHN SCOTT , HODGES PAUL
IPC: H03M7/14 , G06F5/00 , G11B20/14 , H03M7/00 , H03M7/30 , H03M7/40 , H03M7/46 , H04L23/00 , H04L25/49 , H03K13/00
Abstract: Apparatus for converting binary digital data from one form to another according to a variable word length code of fixed rate comprises word position indicating circuitry for indicating predetermined word position states of data in a data storage unit and conversion circuitry for sequentially converting a constant number of input bits at a time into the corresponding number of bits in said other form in dependence upon the contents of the data storage unit and the word position indication. The constant number of bits is less than the number of bits in the longest variable length word in the input data code form. The word position indicating circuitry either generates an updated function representing the current position of the word boundary in the data storage unit or recognizes the boundary from distinctive word ending patterns in the data storage unit.
-
公开(公告)号：CA1021464A
公开(公告)日：1977-11-22
申请号：CA203323
申请日：1974-06-25
Applicant: IBM
Inventor： HODGES PAUL
Abstract: An electrical digital transmission method and circuits for improving recorded or transmitted information density. The embodiment serially modulates signal switching with a separation of at least two adjacent clock periods and not over eight clock periods in any sequence of byte transmissions. A fixed length transmission per byte is used. A serial clock cycle is provided per data byte and may be divided into two clock cycle sections. The first clock period of each section is not available for information modulation switching. The remaining clock periods of each section are available to contain electrical current switchings to encode a part of an information byte by permuting the switchings while maintaining the required switching separation. The first clock period of each section contains a switching only if no information induced switching occurs in its adjacent clock periods. These clock switchings assure an output switching within a maximum number of clock periods equal to the longest of the two sections.
-
公开(公告)号：DE1263088B
公开(公告)日：1968-03-14
申请号：DEJ0027782
申请日：1965-03-26
Applicant: IBM DEUTSCHLAND
Inventor： SCHELER TITUS , GENG ROLAND , KUNDEL GERHARD , HODGES PAUL , UTLEY BRIAN GEORGE
IPC: G11C21/00
-
公开(公告)号：DE69724846T2
公开(公告)日：2004-07-08
申请号：DE69724846
申请日：1997-01-23
Applicant: IBM
Inventor： HODGES PAUL , HURLEY MICHAEL GARWOOD , OUCHI NORMAN KENNETH , SHIH MIEN
Abstract: A data processing system (300, 800, 1000) having multiple independent paths for communication between a host (310, 810, 1010) and a plurality of storage devices (340, 840, 1040) where each path has its own queue (326, 828) for servicing requests generated by the host for accessing the storage devices. Each request is assigned a unique sequential ID before it is stored, along with its unique ID, in all the queues. Each storage device has a "mailbox" register (500) where the ID and the status (520) of the latest request being carried out is stored. Queues are serviced and their status updated based on the content of the mailbox in each storage device. The combination of assigning a unique task ID to each request and a "mailbox" register in each storage device allows the queue in each path to be completely out of sync with each of the queues in the other paths without causing data integrity problems, duplication of requests at the device level, or a need for complex locking schemes to keep the queues in sync with each other.
-
Patent Agency Ranking
公开(公告)号：DE68920523D1
公开(公告)日：1995-02-23
申请号：DE68920523
申请日：1989-08-24
Applicant: IBM
Inventor： EGGENBERGER JOHN SCOTT , HODGES PAUL , PATEL ARVIND MOTIBHAI
Abstract: A method is disclosed for correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise sub-blocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading. A sequence of N sequential parity check bytes is written at the end of each block. After ECC syndromes are generated during reading, parity syndromes are generated by comparing parity check bytes computed from data bytes and check bytes as read with the parity check bytes as written. When a long-burst error occurs, a pointer points to the first of the N consecutive bytes in a block that could have been influenced by the error burst. After correcting correctable errors in all sub-blocks not affected by the N bytes identified by the pointer, and adjusting the parity syndromes for errors thus corrected, the adjusted parity syndromes are used to correct the errors in the N bytes indicated by the pointer. Unused ECC syndromes are then adjusted for errors corrected by the adjusted parity syndromes and used to correct all correctable errors then remaining.
-
公开(公告)号：CA1117661A
公开(公告)日：1982-02-02
申请号：CA325875
申请日：1979-04-19
Applicant: IBM
Inventor： HODGES PAUL , SCHAEUBLE WERNER J , SHAFFER PAUL L
Abstract: ERROR CORRECTING SYSTEM FOR SERIAL BY BYTE DATA A system is disclosed for generating a plurality of error correcting check ECC bytes from a block of data presented to the system in serial by byte form. The system employs a plurality of ECC channels which operate in parallel with the channel generating check bytes from interleaved subsets of the data block. One channel generates an ECC parity check byte for each interleaved subset while another channel generates an ECC locator check byte for each interleaved subset of data. The ECC locator check byte for each subset represents the parity or modulo 2 sum of bit positions which are selected systematically in accordance with a predefined m sequence which is unique to each channel that generates locator check bytes. Error patterns greater than the number of bits in one byte are correctable, as are error patterns which are less than the number of bits in one byte but extend across byte boundaries of two adjacent bytes in different subsets. SA978033
-
公开(公告)号：CA1075817A
公开(公告)日：1980-04-15
申请号：CA223702
申请日：1975-04-02
Applicant: IBM
Inventor： EGGENBERGER JOHN S , HODGES PAUL
IPC: H03M7/14 , G06F5/00 , G11B20/14 , H03M7/00 , H03M7/30 , H03M7/40 , H03M7/46 , H04L23/00 , H04L25/49 , H03K13/24
Abstract: SEQUENTIAL ENCODING AND DECODING OF VARIABLE WORD LENGTH, FIXED RATE DATA CODES A method of encoding or decoding data in a code of variable length words and fixed rate comprises the steps of (1) initially entering a constant number (k) of input bits into a shift register; (2) entering a constant number (m) of input bits into the shift register; (3) encoding or decoding a constant number (n) of bits in response to the contents of the shift register; and (4) repeating steps (2) and (3) until the input bits are exhausted. To complete the encoding or decoding, steps (2) and (3) are further repeated with dummy input bits until (k) dummy bits have been entered into the shift register. The encoding or decoding of (n) bits may be affected by auxiliary state variables which account for the position in the shift register of the boundary between words.
-
公开(公告)号：DE2430685A1
公开(公告)日：1975-01-30
申请号：DE2430685
申请日：1974-06-26
Applicant: IBM
Inventor： HODGES PAUL
Abstract: An electrical digital transmission method and circuits for improving recorded or transmitted information density. The embodiment serially modulates signal switching with a separation of at least two adjacent clock periods and not over eight clock periods in any sequence of byte transmissions. A fixed length transmission per byte is used. A serial clock cycle is provided per data byte and may be divided into two clock cycle sections. The first clock period of each section is not available for information modulation switching. The remaining clock periods of each section are available to contain electrical current switchings to encode a part of an information byte by permuting the switchings while maintaining the required switching separation. The first clock period of each section contains a switching only if no information induced switching occurs in its adjacent clock periods. These clock switchings assure an output switching within a maximum number of clock periods equal to the longest of the two sections.
-
公开(公告)号：DE69724846D1
公开(公告)日：2003-10-23
申请号：DE69724846
申请日：1997-01-23
Applicant: IBM
Inventor： HODGES PAUL , HURLEY MICHAEL GARWOOD , OUCHI NORMAN KENNETH , SHIH MIEN
Abstract: A data processing system (300, 800, 1000) having multiple independent paths for communication between a host (310, 810, 1010) and a plurality of storage devices (340, 840, 1040) where each path has its own queue (326, 828) for servicing requests generated by the host for accessing the storage devices. Each request is assigned a unique sequential ID before it is stored, along with its unique ID, in all the queues. Each storage device has a "mailbox" register (500) where the ID and the status (520) of the latest request being carried out is stored. Queues are serviced and their status updated based on the content of the mailbox in each storage device. The combination of assigning a unique task ID to each request and a "mailbox" register in each storage device allows the queue in each path to be completely out of sync with each of the queues in the other paths without causing data integrity problems, duplication of requests at the device level, or a need for complex locking schemes to keep the queues in sync with each other.
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.019 seconds)
