PATCH-AUF-INTERPOSER PAKET MIT DRAHTLOSER KOMMUNIKATIONSSCHNITTSTELLE

    公开(公告)号:DE112015006965T5

    公开(公告)日:2018-07-05

    申请号:DE112015006965

    申请日:2015-12-02

    Applicant: INTEL CORP

    Abstract: Es wird ein Patch-auf-einem-Interposer- (PoINT) Paket mit einer drahtlosen Kommunikationsschnittstelle beschrieben. Einige Beispiele weisen auf einen Interposer, einen an dem Interposer angebrachten Haupt-Patch, einen an den Patch angebrachten integrierten Haupt-Schaltkreis-Die, einen an den Interposer angebrachten zweiten Patch, und einen Millimeterwellen-Funk-Die, der an dem zweiten Patch angebracht ist und durch den Interposer mit der integrierten Haupt-Schaltkreis-Die verbunden ist, um Daten zwischen dem Haupt-Die und einer externen Komponente zu kommunizieren.

    MULTI-LAYER PACKAGE WITH INTEGRATED ANTENNA

    公开(公告)号:SG11201608264YA

    公开(公告)日:2016-10-28

    申请号:SG11201608264Y

    申请日:2014-05-06

    Applicant: INTEL CORP

    Abstract: Embodiments of the present disclosure describe a multi-layer package with antenna and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a first layer having a first side and a second side disposed opposite to the first side a second layer coupled with the first side of the first layer, one or more antenna elements coupled with the second layer and a third layer coupled with the second side of the first layer, wherein the first layer is a reinforcement layer having a tensile modulus that is greater than a tensile modulus of the second layer and the third layer. Other embodiments may be described and/or claimed.

    Die package with superposer substrate for passive components

    公开(公告)号:GB2520149A

    公开(公告)日:2015-05-13

    申请号:GB201416330

    申请日:2014-09-16

    Applicant: INTEL CORP

    Abstract: A semiconductor die package 100 includes active circuitry 104 on a front side of a die 102, such as a system on chip (SoC) die or radio frequency (RF) die which includes a silicon substrate, and a separate component substrate 110 near a back side of the die to carry passive components 112 which may include high Q inductors, transformers, capacitors and resistors. The component substrate may be bump bonded to the back surface of the die. A conductive path, which may comprise a through silicon via (TSV) 116 connects passive components to the active circuitry on the die. A package substrate 106 may be positioned over the front side of the die and connected through a mold compound 108 to the die 102. A multi-die stack may include a second die on the opposite side of the component substrate to the first die (see Fig. 2; 222). The component substrate may extend laterally beyond the die allowing direct connection between the component substrate and package substrate by through mold vias (TMVs) (Fig. 3; 334) for power connections.

Patent Agency Ranking