公开(公告)号：US11307628B2

公开(公告)日：2022-04-19

申请号：US15589769

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/3203 ,  G06F1/26

Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

公开(公告)号：US10474218B2

公开(公告)日：2019-11-12

申请号：US16223794

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F12/00 ,  G06F1/3234 ,  G06F12/0864 ,  G06F12/084 ,  G06F1/28 ,  G06F12/0802 ,  G06F1/3287 ,  G06F12/0846

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20190011975A1

公开(公告)日：2019-01-10

申请号：US16044994

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/32 ,  G06F12/0846 ,  G06F1/28 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0864

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20170308146A1

公开(公告)日：2017-10-26

申请号：US15589769

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3206 ,  G06F1/26 ,  G06F1/3203

Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

公开(公告)号：US09785226B2

公开(公告)日：2017-10-10

申请号：US14866874

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Oren Lamdan ,  Alon Naveh

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/20 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F9/30

CPC classification number: G06F1/3287 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/30083 ,  G06F9/3814 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

公开(公告)号：US09639372B2

公开(公告)日：2017-05-02

申请号：US13730565

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3891

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

公开(公告)号：US20170024210A1

公开(公告)日：2017-01-26

申请号：US15175881

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

IPC: G06F9/30 ,  G06F9/46 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/461

Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.

Abstract translation: 处理器可以节省微架构上下文以提高代码执行和电源管理的效率。 执行保存指令以在停止进程的执行的上下文切换时将微架构状态和处理器的体系结构状态存储在存储器的公共缓冲器中。 微架构状态包含执行该过程所产生的性能数据。 执行恢复指令以在恢复执行该过程时从公共缓冲器检索微架构状态和架构状态。 电源管理硬件然后使用微架构状态作为恢复执行的中间起点。

公开(公告)号：US20170010648A1

公开(公告)日：2017-01-12

申请号：US15270206

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Shaun M. Conrad ,  William Knolla ,  Douglas R. Moran ,  Sm M. Rahman ,  Jawad Haj-Yihia ,  Alon Naveh ,  Ohad Falik

IPC: G06F1/32 ,  G06F13/40

CPC classification number: G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/40 ,  G06F13/4027 ,  G06F13/4068 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/172

Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.

Abstract translation: 处理器包括至少一个核心，功率控制单元和与外围控制器耦合的第一互连。 第一互连是提供用于从处理器到外围控制器的第一电力管理数据的通信的第一单向通信路径。 描述和要求保护其他实施例。

公开(公告)号：US20160335020A1

公开(公告)日：2016-11-17

申请号：US15219183

申请日：2016-07-25

Applicant: Intel Corporation

Inventor： Inder M. Sodhi ,  Alon Naveh ,  Doron Rajway ,  Ryan D. Wells ,  Eric C. Samson

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/3206 ,  G06F1/3278 ,  G06F1/3287 ,  G06F3/0634 ,  G06F3/0673 ,  Y02D10/157 ,  Y02D10/171

Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

Abstract translation: 描述了能量效率和能量节约的系统，装置和方法的实施例，包括实现设备的自主的基于硬件的深度断电。 在一个实施例中，系统包括与设备和静态存储器耦合的设备，静态存储器和功率控制单元。 该系统还包括功率控制单元的深度掉电逻辑，用于监视设备的状态，并且当设备空闲时将设备传送到深度断电状态。 在系统中，当处于深功率关闭状态时，器件消耗的功率小于空闲状态。

公开(公告)号：US09239789B2

公开(公告)日：2016-01-19

申请号：US14741624

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Zeev Offen ,  Alon Naveh ,  Iris Sorani

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0806 ,  G06F9/3009 ,  G06F12/084 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/284 ,  G06F2212/62

Abstract: A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle.

Abstract translation: 公开了一种用于在分布式高速缓存架构中进行监视和等待的方法和装置。 一个实施例包括向存储对应于该地址的数据的分布式高速缓存的一部分发送对地址的MONITOR请求的执行线程。 在分布式缓存部分，MONITOR请求和关联的推测状态被本地记录在执行线程上。 执行线程然后发出地址的MWAIT指令。 在分布式缓存部分，为执行线程记录MWAIT和关联的等待触发状态。 当在分布式高速缓存部分接收到与该地址匹配的写入请求时，监视器 - 唤醒事件然后被发送到执行线程，并且用于该执行线程的分布式高速缓存部分处的关联监视状态可以被重置为空闲。