公开(公告)号：US20180095802A1

公开(公告)日：2018-04-05

申请号：US15283006

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Hang T. Nguyen ,  Gordon McFadden ,  Pradeepsunder Ganesh ,  Stephen Thomas Palermo ,  Travis J. White ,  Ashok Raj ,  Vivek Garg ,  Dhruv Singh

IPC: G06F9/50

CPC classification number: G06F9/5044 ,  G06F9/5094 ,  Y02D10/22

Abstract: In one embodiment, a method comprises determining, at a plurality of instances in time, a value of at least one stress characteristic of a hardware resource; determining an accumulated stress value of the hardware resource, the accumulated stress value comprising the sum of a plurality of incremental stress values, an incremental stress value determined based on the value of the at least one stress characteristic at a particular instance in time; and generating a first stress indicator in response to a determination that the accumulated stress value of the hardware resource is greater than a first threshold stress value associated with the hardware resource.

公开(公告)号：US20170344414A1

公开(公告)日：2017-11-30

申请号：US15168999

申请日：2016-05-31

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Theodros Yigzaw

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772

Abstract: In accordance with implementations disclosed herein, there is provided systems and methods for enabling error status and reporting in a machine check environment. A processing device includes an error status register and an error status component communicably coupled to the error status register. The error status component determines that a machine check error (MCE) is a first correctable error (CE) and sets a first error status corresponding to the first CE in the error status register based on a threshold value. The threshold value is based on a type of the first CE.

公开(公告)号：US20170123872A1

公开(公告)日：2017-05-04

申请号：US14925131

申请日：2015-10-28

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Mohan J. Kumar ,  Hisham Shafi ,  Ron Gabor ,  Ashok Raj

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/079 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/3016 ,  G06F11/0721 ,  G06F11/0784 ,  G06F11/0787 ,  G06F11/0793 ,  G06F12/00 ,  G06F12/0246

Abstract: In one embodiment, a processor includes a core having a fetch unit to fetch instructions, a decode unit to decode the instructions, and one or more execution units to execute the instructions. The core may further include: a first pair of block address range registers to store a start location and an end location of a block range within a non-volatile block storage coupled to the processor; and a block status storage to store an error indicator responsive to an occurrence of an error within the block range during a block operation. Other embodiments are described and claimed.

公开(公告)号：US09389942B2

公开(公告)日：2016-07-12

申请号：US14057485

申请日：2013-10-18

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Narayan Ranganathan

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0706 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/1417 ,  G06F2201/805

Abstract: A computing system can include a machine check counter (MCC) including a current value. The current value indicates a system reboot resetting hardware of the computing system. The machine check counter includes a model specific register including a counter indicating the current value, the current value to be incremented upon the system reboot.

Abstract translation: 计算系统可以包括包括当前值的机器检查计数器（MCC）。 当前值表示计算系统的系统重新启动重置硬件。 机器检查计数器包括一个特定于型号的寄存器，包括一个指示当前值的计数器，当系统重启时增加的当前值。

公开(公告)号：US12164444B2

公开(公告)日：2024-12-10

申请号：US17357829

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Rajesh Sankaran ,  Rupin Vakharwala ,  Utkarsh Y. Kakaiya

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/455

Abstract: Techniques and mechanisms for an input-output memory management module (IOMMU) to indicate to software whether a page request by an endpoint device is to be serviced. In an embodiment, the IOMMU receives from the endpoint device a response to an invalidation wait message. Based on the response, the IOMMU provides first information which indicates to software that page requests have been flushed from the endpoint device. Page request message from the endpoint device are compatible with an interface standard which also comprises a stop marker message type. The first information is provided independent of the endpoint device providing any message which is of the stop marker message type. In another embodiment, the first information includes a drain marker generated by the IOMMU, or a snapshot of an address corresponding to an end of a page request queue.

公开(公告)号：US11740931B2

公开(公告)日：2023-08-29

申请号：US17651906

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Ashok Raj ,  Rajesh Sankaran

IPC: G06F9/48 ,  G06F13/28 ,  G06F9/30

CPC classification number: G06F9/4812 ,  G06F9/30101 ,  G06F9/485 ,  G06F13/28

Abstract: A processing device is provided. The processing device comprises an interface configured to receive information about an operation state of a surrogate processor. Further, the processing device comprises a processing circuitry configured to control the interface and to decide whether an interrupt addressed to the processing circuitry is processed by the processing circuitry or redirected to the surrogate processing circuitry based on an operation state of the processing circuitry and the surrogate processing circuitry.

公开(公告)号：US20230205563A1

公开(公告)日：2023-06-29

申请号：US17560826

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Rajesh Sankaran ,  Anjali Singhai Jain ,  Patrick Maloney

IPC: G06F9/455 ,  G06F12/0831

CPC classification number: G06F9/45558 ,  G06F12/0835 ,  G06F2009/45583 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2009/45591

Abstract: Systems, methods, and devices for efficient I/O page fault handling are provided. A system may include a peripheral device that accesses guest memory of a virtual machine using direct memory access (DMA) and a processing device that that runs the virtual machine. The processing device may include a buffer allocated to receive a payload from the peripheral device while an input/output page fault corresponding to a page of the guest memory is resolved. The processing device may also include an input/output page fault queue to store a descriptor corresponding to the input/output page fault and a fault buffer queue to store a descriptor corresponding to a location of the buffer allocated to receive the payload while the input/output page fault is resolved.

公开(公告)号：US20220414029A1

公开(公告)日：2022-12-29

申请号：US17357829

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Rajesh Sankaran ,  Rupin Vakharwala ,  Utkarsh Y. Kakaiya

IPC: G06F13/16 ,  G06F13/42

Abstract: Techniques and mechanisms for an input-output memory management module (IOMMU) to indicate to software whether a page request by an endpoint device is to be serviced. In an embodiment, the IOMMU receives from the endpoint device a response to an invalidation wait message. Based on the response, the IOMMU provides first information which indicates to software that page requests have been flushed from the endpoint device. Page request message from the endpoint device are compatible with an interface standard which also comprises a stop marker message type. The first information is provided independent of the endpoint device providing any message which is of the stop marker message type. In another embodiment, the first information includes a drain marker generated by the IOMMU, or a snapshot of an address corresponding to an end of a page request queue.

公开(公告)号：US20210271481A1

公开(公告)日：2021-09-02

申请号：US17253053

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Kun Tian ,  Sanjay Kumar ,  Ashok Raj ,  Yi Liu ,  Rajesh M. Sankaran ,  Philip R. Lantz

IPC: G06F9/34 ,  G06F9/455 ,  G06F9/38 ,  G06F13/42 ,  G06F12/1009

Abstract: Process address space identifier virtualization uses hardware paging hint. The processing device (100) comprising: a processing core (110); and a translation circuit coupled to the processing core, the translation circuit to: receive a workload instruction from a guest application being executed by the processing device, the workload instruction comprising an untranslated guest process address space identifier (gPASID), a workload for an input/output (I/O) target device, and an identifier of a submission register on the I/O target device (410), access a paging data structure (PDS) associated with the guest application to retrieve a page table entry corresponding to the gPASID and the identifier of the submission register (420), determine a value of an I/O hint bit of the page table entry corresponding to the gPASID and the identifier of the submission register (430), responsive to determining that the I/O hint bit is enabled, keep the untranslated gPASID in the workload instruction (440), and provide the workload instruction to a work queue of the I/O target device (450)

公开(公告)号：US11068339B2

公开(公告)日：2021-07-20

申请号：US16417555

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.