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公开(公告)号：US20170149926A1
公开(公告)日：2017-05-25
申请号：US15426718
申请日：2017-02-07
Applicant: Intel Corporation
Inventor： Ren Wang , Sameh Gobriel , Christian Maciocco , Tsung-Yuan C. Tai , Ben-Zion Friedman , Hang T. Nguyen , Namakkal N. Venkatesan , Michael A. O'Hanlon , Shrikant M. Shah , Sanjeev Jain
IPC: H04L29/08 , H04L12/743 , H04L12/721 , H04L12/24 , H04L12/741
CPC classification number: H04L67/2852 , H04L41/0893 , H04L45/38 , H04L45/745 , H04L45/7453 , H04L49/00
Abstract: Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.
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2.发明申请HARDWARE PROCESSORS AND METHODS TO PERFORM SELF-MONITORING DIAGNOSTICS TO PREDICT AND DETECT FAILURE 审中-公开硬件处理器和执行自我诊断诊断和检测故障的方法公开(公告)号：US20160378628A1
公开(公告)日：2016-12-29
申请号：US14752821
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Hang T. Nguyen , Gordon McFadden , Travis J. White , Scott P. Bobholz , Edwin Verplanke , Steven C. Franks , Vivek Garg , Ashok Raj , Guy G. Sotomayor , Jose A. Vargas , Pradeepsunder Ganesh , Stephen T. Palermo
IPC: G06F11/273 , G06F11/22
CPC classification number: G06F11/2236 , G06F11/008 , G06F11/27
Abstract: Hardware processors and methods to perform self-monitoring diagnostics to predict and detect failure are described. In one embodiment, a hardware processor includes a plurality of cores, and a diagnostic hardware unit to isolate a core of the plurality of cores at run-time, perform a stress test on an isolated core, determine a stress factor from a result of the stress test, and store the stress factor in a data storage device.
Abstract translation: 描述了执行自我监视诊断以预测和检测故障的硬件处理器和方法。 在一个实施例中，硬件处理器包括多个核心，以及诊断硬件单元，用于在运行时间隔离所述多个核心的核心，在隔离的核心上执行压力测试，从所述核心的结果中确定压力因素 压力测试，并将应力因子存储在数据存储设备中。
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公开(公告)号：US10936449B2
公开(公告)日：2021-03-02
申请号：US15465247
申请日：2017-03-21
Applicant: Intel Corporation
Inventor： Hang T. Nguyen , Stephen T. Palermo , John J. Browne , Chris MacNamara , Pradeepsunder Ganesh
Abstract: Discussed herein are component redundancy systems, devices, and methods. A method to transfer a workload from a first component to a second component of a same device may include monitoring a wear indicator associated with the first component, and in response to an indication that the first component is stressed based on the wear indicator, transferring a workload of the first component to the second component.
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公开(公告)号：US09983661B2
公开(公告)日：2018-05-29
申请号：US15135670
申请日：2016-04-22
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
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公开(公告)号：US20180095802A1
公开(公告)日：2018-04-05
申请号：US15283006
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Hang T. Nguyen , Gordon McFadden , Pradeepsunder Ganesh , Stephen Thomas Palermo , Travis J. White , Ashok Raj , Vivek Garg , Dhruv Singh
IPC: G06F9/50
CPC classification number: G06F9/5044 , G06F9/5094 , Y02D10/22
Abstract: In one embodiment, a method comprises determining, at a plurality of instances in time, a value of at least one stress characteristic of a hardware resource; determining an accumulated stress value of the hardware resource, the accumulated stress value comprising the sum of a plurality of incremental stress values, an incremental stress value determined based on the value of the at least one stress characteristic at a particular instance in time; and generating a first stress indicator in response to a determination that the accumulated stress value of the hardware resource is greater than a first threshold stress value associated with the hardware resource.
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Patent Agency Ranking
6.发明授权Mechanism to provide workload and configuration-aware deterministic performance for microprocessors 有权为微处理器提供工作负载和配置感知确定性性能的机制公开(公告)号：US09417681B2
公开(公告)日：2016-08-16
申请号：US14697541
申请日：2015-04-27
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
IPC: G06F15/177 , G06F1/32 , G06F1/00 , G06F1/20
CPC classification number: G06F1/3243 , G06F1/206 , G06F1/28 , G06F1/3206 , Y02D10/152
Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
Abstract translation: 装置的一个实施例包括具有处理器和裸片上非易失性存储资源的半导体芯片。 片上非易失性存储器可以为处理器的相同性能状态的不同配置和处理器的使用情况存储不同的适当的性能相关信息。
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公开(公告)号：US20160103474A1
公开(公告)日：2016-04-14
申请号：US14974064
申请日：2015-12-18
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
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公开(公告)号：US09983660B2
公开(公告)日：2018-05-29
申请号：US14974064
申请日：2015-12-18
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
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公开(公告)号：US09983659B2
公开(公告)日：2018-05-29
申请号：US14966273
申请日：2015-12-11
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
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公开(公告)号：US09348387B2
公开(公告)日：2016-05-24
申请号：US14570100
申请日：2014-12-15
Applicant: Intel Corporation
Inventor： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
CPC classification number: G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.
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