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51.
公开(公告)号:US20230114263A1
公开(公告)日:2023-04-13
申请号:US18065241
申请日:2022-12-13
Applicant: Intel Corporation
Inventor: Ren Wang , Poonam Shidlyali , Tsung-Yuan Tai
Abstract: Systems, apparatuses and methods may provide for technology that uses centralized hardware to detect a local allocation request associated with a local thread, detect a remote allocation request associated with a remote thread, wherein the remote allocation request bypasses a remote operating system, and process the local allocation request and the remote allocation request with respect to central heap, wherein the central heap is shared by the local thread and the remote thread. The local allocation request and the remote allocation request may include one or more of a first request to allocate a memory block of a specified size, a second request to allocate multiple memory blocks of a same size, a third request to resize a previously allocated memory block, or a fourth request to deallocate the previously allocated memory block.
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公开(公告)号:US11201940B2
公开(公告)日:2021-12-14
申请号:US15862311
申请日:2018-01-04
Applicant: Intel Corporation
Inventor: Yipeng Wang , Ren Wang , Antonio Fischetti , Sameh Gobriel , Tsung-Yuan C. Tai
Abstract: Technologies for flow rule aware exact match cache compression include multiple computing devices in communication over a network. A computing device reads a network packet from a network port and extracts one or more key fields from the packet to generate a lookup key. The key fields are identified by a key field specification of an exact match flow cache. The computing device may dynamically configure the key field specification based on an active flow rule set. The computing device may compress the key field specification to match a union of non-wildcard fields of the active flow rule set. The computing device may expand the key field specification in response to insertion of a new flow rule. The computing device looks up the lookup key in the exact match flow cache and, if a match is found, applies the corresponding action. Other embodiments are described and claimed.
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公开(公告)号:US11088951B2
公开(公告)日:2021-08-10
申请号:US15638102
申请日:2017-06-29
Applicant: Intel Corporation
Inventor: Ren Wang , Tsung-Yuan C. Tai , Yipeng Wang , Sameh Gobriel
IPC: H04L12/743 , H04L12/851 , H04L12/741 , H04L29/12 , H04L12/751
Abstract: Apparatus, methods, and systems for tuple space search-based flow classification using cuckoo hash tables and unmasked packet headers are described herein. A device can communicate with one or more hardware switches. The device can include memory to store hash table entries of a hash table. The device can include processing circuitry to perform a hash lookup in the hash table. The lookup can be based on an unmasked key include in a packet header corresponding to a received data packet. The processing circuitry can retrieve an index pointing to a sub-table, the sub-table including a set of rules for handling the data packet. Other embodiments are also described.
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54.
公开(公告)号:US10904161B2
公开(公告)日:2021-01-26
申请号:US16218262
申请日:2018-12-12
Applicant: Intel Corporation
Inventor: Ren Wang , Ahmad A. Samih , Christian Maciocco , Andrew Brown , Tsung-Yuan C. Tai
IPC: H04L12/801 , H04L12/24 , H04L5/14 , H04W84/18 , H04L12/927 , H04L12/725 , H04L12/931 , H04L12/863 , H04L12/851 , H04L12/841
Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for routing data packets in a quality of service (QoS) enabled content-based network or interconnect fabric. Various embodiments describe how to manage data flow based on content-based attribute vectors (AVs) indicating QoS requirements with respect to the data packets in networking or platform interconnects. A dynamic scheduling based on AV information may improve trafficking efficiency and optimize system performance.
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公开(公告)号:US10805229B2
公开(公告)日:2020-10-13
申请号:US16410442
申请日:2019-05-13
Applicant: Intel Corporation
Inventor: Ren Wang , Tsung-Yuan Charles Tai , Jr-Shian Tsai
IPC: H04L12/925 , H04L12/911 , H04N1/333 , H04L1/18 , H04L12/835 , H04L12/12 , H04L29/08
Abstract: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request that at least one network node generate, at least in part, information. The information may be to permit selection, at least in part, of (1) at least one power consumption state of the at least one network node, and (2) at least one time period. The at least one time period may be to elapse, after receipt by at least one other network node of at least one packet, prior to requesting at least one change in the at least one power consumption state. The at least one packet may be to be transmitted to the at least one network node. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.
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公开(公告)号:US20200285578A1
公开(公告)日:2020-09-10
申请号:US16822939
申请日:2020-03-18
Applicant: Intel Corporation
Inventor: Ren Wang , Joseph Nuzman , Samantika S. Sury , Andrew J. Herdrich , Namakkal N. Venkatesan , Anil Vasudevan , Tsung-Yuan C. Tai , Niall D. McDonnell
IPC: G06F12/0831 , G06F12/084 , G06F12/0811
Abstract: Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.
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公开(公告)号:US10552153B2
公开(公告)日:2020-02-04
申请号:US15476302
申请日:2017-03-31
Applicant: Intel Corporation
Inventor: Ren Wang , Chunhui Zhang , Qixiong J. Bian , Bret L. Toll , Jason W. Brandt
IPC: G06F9/30 , G06F12/0842 , G06F12/0875 , G06F12/0891 , G06F13/28 , G06F12/084
Abstract: Method and apparatus for efficient range-based memory write back is described herein. One embodiment of an apparatus includes a system memory, a plurality of hardware processor cores each of which includes a first cache, a decoder circuitry to decode an instruction having fields for a first memory address and a range indicator, and an execution circuitry to execute the decoded instruction. Together, the first memory address and the range indicator define a contiguous region in the system memory that includes one or more cache lines. An execution of the decoded instruction causes any instances of the one or more cache lines in the first cache to be invalidated. Additionally, any invalidated instances of the one or more cache lines that are dirty are to be stored to system memory.
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公开(公告)号:US10445271B2
公开(公告)日:2019-10-15
申请号:US14987676
申请日:2016-01-04
Applicant: Intel Corporation
Inventor: Ren Wang , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Yipeng Wang , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson
IPC: G06F13/37 , G06F12/0811 , G06F13/16 , G06F12/0868 , G06F12/04 , G06F9/38
Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.
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公开(公告)号:US10313240B2
公开(公告)日:2019-06-04
申请号:US15632592
申请日:2017-06-26
Applicant: Intel Corporation
Inventor: Sameh Gobriel , Wei Shen , Tsung-Yuan C. Tai , Ren Wang
IPC: H04L12/927 , H04L12/743 , H04L12/741 , H04L29/12 , H04L12/755
Abstract: Technologies for efficient network flow classification include a computing device that receives a network packet that includes a header. The computing device generates a vector Bloom filter (VBF) key as a function of the header and searches multiple VBFs for a VBF that matches the VBF key. Each VBF is associated with a flow sub-table that includes one or more flow rules. Each flow sub-table is associated with a mask length. If a matching VBF is found, the computing device searches the corresponding flow sub-table for a flow rule that matches a masked header of the network packet. If no matching VBF is found or if no matching flow rule is found, the computing device searches all of the flow sub-tables for a flow rule that matches the header. The computing device applies a flow action of a matching flow rule. Other embodiments are described and claimed.
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公开(公告)号:US20190012200A1
公开(公告)日:2019-01-10
申请号:US15645226
申请日:2017-07-10
Applicant: INTEL CORPORATION
Inventor: Christopher B. Wilkerson , Karl I. Taht , Ren Wang , James J. Greensky , Tsung-Yuan C. Tai
IPC: G06F9/48
Abstract: A computing platform, including: an execution unit to execute a program, the program including a first phase and a second phase; and a quick response module (QRM) to: receive a program phase signature for the first phase; store the program phase signature in a pattern match action (PMA) table; identify entry of the program into the first phase via the PMA; and apply an optimization to the computing platform.
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