公开(公告)号：US12255830B2

公开(公告)日：2025-03-18

申请号：US18201068

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Kiran A. Patil ,  Arun Chekhov Ilango

IPC: H04L47/50 ,  H04L47/24 ,  H04L47/2475 ,  H04L49/90 ,  H04L43/10

Abstract: There is disclosed in one example a network interface card (NIC), comprising: an ingress interface to receive incoming traffic; a plurality of queues to queue incoming traffic; an egress interface to direct incoming traffic to a plurality of server applications; and a queuing engine, including logic to: uniquely associate a queue with a selected server application; receive an incoming network packet; determine that the selected server application may process the incoming network packet; and assign the incoming network packet to the queue.

公开(公告)号：US12153962B2

公开(公告)日：2024-11-26

申请号：US16849915

申请日：2020-04-15

Applicant: Intel Corporation

Inventor： Ziye Yang ,  James R. Harris ,  Kiran Patil ,  Benjamin Walker ,  Sudheer Mogilappagari ,  Yadong Li ,  Mark Wunderlich ,  Anil Vasudevan

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/54 ,  G06F13/22 ,  H04L67/1097 ,  H04L69/16

Abstract: The disclosure concerns at least one processor that can execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers. The disclosure concerns at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group and not the first polling group.

公开(公告)号：US11797333B2

公开(公告)日：2023-10-24

申请号：US16710556

申请日：2019-12-11

Applicant: Intel Corporation

Inventor： Linden Cornett ,  Anil Vasudevan ,  Parthasarathy Sarangam ,  Kiran Patil

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4812 ,  G06F9/5077 ,  G06F2209/5011

Abstract: Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located. After asserting an interrupt, an RX queue may be auto-masked to prevent generation of additional events when new descriptors are enqueued in the RX queue.

公开(公告)号：US20230300078A1

公开(公告)日：2023-09-21

申请号：US18201068

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Kiran A. Patil ,  Arun Chekhov Ilango

IPC: H04L47/50 ,  H04L47/2475 ,  H04L47/24 ,  H04L49/90

CPC classification number: H04L47/50 ,  H04L47/2475 ,  H04L47/24 ,  H04L49/9068 ,  H04L49/90 ,  H04L43/10

Abstract: There is disclosed in one example a network interface card (NIC), comprising: an ingress interface to receive incoming traffic; a plurality of queues to queue incoming traffic; an egress interface to direct incoming traffic to a plurality of server applications; and a queuing engine, including logic to: uniquely associate a queue with a selected server application; receive an incoming network packet; determine that the selected server application may process the incoming network packet; and assign the incoming network packet to the queue.

公开(公告)号：US11327894B2

公开(公告)日：2022-05-10

申请号：US16834845

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US11063884B2

公开(公告)日：2021-07-13

申请号：US16554064

申请日：2019-08-28

Applicant: Intel Corporation

Inventor： Ilango Ganga ,  Alain Gravel ,  Thomas Lovett ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson

IPC: H04L12/939 ,  H04L1/16 ,  H04L12/947 ,  H04L12/861

Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.

公开(公告)号：US20200162396A1

公开(公告)日：2020-05-21

申请号：US16773801

申请日：2020-01-27

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Kiran A. Patil ,  Arun Chekhov Ilango

IPC: H04L12/863 ,  H04L12/859 ,  H04L12/851 ,  H04L12/861

Abstract: There is disclosed in one example a network interface card (NIC), comprising: an ingress interface to receive incoming traffic; a plurality of queues to queue incoming traffic; an egress interface to direct incoming traffic to a plurality of server applications; and a queuing engine, including logic to: uniquely associate a queue with a selected server application; receive an incoming network packet; determine that the selected server application may process the incoming network packet; and assign the incoming network packet to the queue.

公开(公告)号：US10547559B2

公开(公告)日：2020-01-28

申请号：US14998138

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Kiran A. Patil ,  Arun Chekhov Ilango

IPC: H04L12/28 ,  H04L12/863 ,  H04L12/26

Abstract: In an example, there is disclosed a computing apparatus, having: a network interface configured to provide a plurality of queues; an application; and one or more logic elements comprising a queuing engine to: inspect an incoming packet; and assign the incoming packet to a dedicated queue for the application based on a classifier. There is also disclosed a method of providing a queuing engine, and one or more tangible, non-transitory computer-readable storage mediums having stored thereon executable instructions for providing a queuing engine.

公开(公告)号：US20190391856A1

公开(公告)日：2019-12-26

申请号：US16018712

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Anil Vasudevan

IPC: G06F9/52

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to process a plurality of descriptors from a queue, determine that a descriptor is a barrier descriptor, stop the processing of plurality of descriptors from the queue, extract a global address from the barrier descriptor, communicate a message to the global address that causes a counter associated with the global address to be incremented, determine contents of a counter at the global address, perform an action when the contents of the counter at the global address satisfies a threshold, and continue to process descriptors from the queue.

公开(公告)号：US10205667B2

公开(公告)日：2019-02-12

申请号：US15614455

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Ilango Ganga ,  Alain Gravel ,  Thomas D. Lovett ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson

IPC: H04L12/851

Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.