公开(公告)号：US09690716B2

公开(公告)日：2017-06-27

申请号：US14621654

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Sheng Li ,  Sanjay Kumar ,  Victor W. Lee ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor

IPC: G06F12/08 ,  G06F12/1045 ,  G06F12/0891

CPC classification number: G06F12/1045 ,  G06F9/467 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/69

Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent cache, wherein the transaction is to create a mapping from a virtual address space to a memory region identified by a memory region identifier (MRID) in the persistent memory, and tag a cache line of the non-persistent cache with the MRID, in which the cache line is associated with a cache line status, and a cache controller, in response to detecting a failure event, to selectively evict contents of the cache line to the memory region identified by the MRID based on the cache line status.