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    Disaggregated computing for distributed confidential computing environment
    52.
    发明授权
    Disaggregated computing for distributed confidential computing environment 有权

    公开(公告)号：US12164973B2

    公开(公告)日：2024-12-10

    申请号：US18511296

    申请日：2023-11-16

    Applicant: Intel Corporation

    Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

    IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

    Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.

    Memory and storage pool interfaces
    53.
    发明授权
    Memory and storage pool interfaces 有权

    公开(公告)号：US12086446B2

    公开(公告)日：2024-09-10

    申请号：US17031721

    申请日：2020-09-24

    Applicant: Intel Corporation

    Inventor： Sujoy Sen ,  Thomas E. Willis ,  Durgesh Srivastava ,  Marcelo Cintra ,  Bassam N. Coury ,  Donald L. Faw ,  Francois Dugast

    IPC: G06F3/06

    CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067

    Abstract: Examples herein relate to a system capable of coupling to a remote memory pool, the system comprising: a memory controller and an interface to a connection, the interface coupled to the memory controller. In some examples, the interface is to translate a format of a memory access request to a format accepted by the memory controller and the memory controller is to provide the translated memory access request in a format accepted by a media. In some examples, a controller is to measure a number of addressable regions that are least accessed and cause at least one of the least accessed regions to be evicted to a local or remote memory device with relatively higher latency. In some examples, a remote access manager is to: determine if a region of addressable memory associated with a memory address for an access request is stored in the memory; based on the region of addressable memory associated with the memory address being stored in the memory, determine if a sub-region of addressable memory associated with the memory address is available for access from the memory, wherein the sub-region comprises less than an entirety of the region; and based on the sub-region of addressable memory being available for access from the memory, provide a physical address for use to access data from the sub-region in the memory and copy the data to the cache.

    DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVIRONMENT
    54.
    发明公开
    DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVIRONMENT 审中-公开

    公开(公告)号：US20240184639A1

    公开(公告)日：2024-06-06

    申请号：US18538171

    申请日：2023-12-13

    Applicant: Intel Corporation

    Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

    IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

    CPC classification number: G06F9/5083 ,  G06F9/3814 ,  G06F9/5027 ,  G06T1/20 ,  G06T1/60

    Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.

    DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVIRONMENT
    55.
    发明公开
    DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVIRONMENT 审中-公开

    公开(公告)号：US20240086258A1

    公开(公告)日：2024-03-14

    申请号：US18511296

    申请日：2023-11-16

    Applicant: Intel Corporation

    Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

    IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

    CPC classification number: G06F9/5083 ,  G06F9/3814 ,  G06F9/5027 ,  G06T1/20 ,  G06T1/60

    Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.

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