公开(公告)号：US11151769B2

公开(公告)日：2021-10-19

申请号：US16537140

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Darrel Palke ,  Sherine Abdelhak ,  Jill Boyce ,  Varghese George ,  Scott Janus ,  Adam Lake ,  Zhijun Lei ,  Zhengmin Li ,  Mike Macpherson ,  Carl Marshall ,  Selvakumar Panneer ,  Prasoonkumar Surti ,  Karthik Veeramani ,  Deepak Vembar ,  Vallabhajosyula Srinivasa Somayazulu

IPC: G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06T17/20 ,  G06N3/08 ,  G06T15/40

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

公开(公告)号：US20200334200A1

公开(公告)日：2020-10-22

申请号：US16869223

申请日：2020-05-07

Applicant: Intel Corporation

Inventor： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC: G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200160534A1

公开(公告)日：2020-05-21

申请号：US16688403

申请日：2019-11-19

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  John G. Gierach ,  Gabor Liktor ,  Andrew T. Lauritzen

IPC: G06T7/194 ,  H04N19/597 ,  G06T7/11 ,  G06T7/00 ,  G06T15/20 ,  H04N21/00 ,  G06T15/50 ,  H04N21/4402 ,  H04N21/2343 ,  H04N19/436 ,  H04N19/167 ,  H04N21/478 ,  H04N19/132 ,  H04N21/81 ,  H04N19/587 ,  H04N19/46

Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.

公开(公告)号：US20180300903A1

公开(公告)日：2018-10-18

申请号：US15489068

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： John G. Gierach ,  Hugues Labbe ,  Tomer Bar-On ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Philip R. Laws ,  Devan Burke ,  Abhishek R. Appu ,  Peter L. Doyle ,  Elmoustapha Ould-Ahmed-Vall ,  Travis T. Schluessler ,  Altug Koker

IPC: G06T9/00 ,  G06T1/20 ,  G06T7/194 ,  G09G3/00 ,  G06T15/20 ,  G06T15/50 ,  G06T1/60

Abstract: Systems, apparatuses, and methods may provide for technology to render and compress stereoscopic graphical data. In one example, the technology identifies, from graphical data associated with a stereoscopic image defined by a first perspective view and a second perspective view, a background region and a foreground region of a graphical scene in the stereoscopic image, renders graphical data of the identified background region for the first perspective view, and compresses the rendered graphical data.

公开(公告)号：US20180300145A1

公开(公告)日：2018-10-18

申请号：US15488988

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0862

CPC classification number: G06F12/0862 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3887 ,  G06F12/0811 ,  G06F12/0855 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/455 ,  G06F2212/602 ,  G06F2212/6024 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

公开(公告)号：US20180300098A1

公开(公告)日：2018-10-18

申请号：US15489096

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Jeffery S. Boles ,  Adam T. Lake ,  David M. Cimini ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Wenyin Fu ,  Nikos Kaburlasos ,  Prasoonkumar Surti ,  Bhushan M. Borole

IPC: G06F3/14 ,  H04L29/06

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

公开(公告)号：US20180288423A1

公开(公告)日：2018-10-04

申请号：US15476990

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  ElMoustapha Ould-Ahmed-Vall ,  James M. Holland

IPC: H04N19/167 ,  H04N19/186 ,  H04N19/597 ,  G06T9/00 ,  H04N19/436 ,  G06T11/60

CPC classification number: G06T11/60 ,  G06T9/00 ,  H04N19/124 ,  H04N19/167 ,  H04N19/17 ,  H04N19/436 ,  H04N19/503

Abstract: An embodiment of a graphics apparatus may include a focus identifier to identify a focus area, and a color compressor to selectively compress color data based on the identified focus area. Another embodiment of a graphics apparatus may include a motion detector to detect motion of a real object, a motion predictor to predict a motion of the real object, and an object placer to place a virtual object relative to the real object based on the predicted motion of the real object. Another embodiment of a graphics apparatus may include a frame divider to divide a frame into viewports, a viewport prioritizer to prioritize the viewports, a renderer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter to transmit a completed rendered viewport. Other embodiments are disclosed and claimed.

公开(公告)号：US20240177395A1

公开(公告)日：2024-05-30

申请号：US18324611

申请日：2023-05-26

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC: G06T15/00 ,  G06T15/30 ,  G06T15/40

CPC classification number: G06T15/005 ,  G06T15/30 ,  G06T15/40

Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US20240161356A1

公开(公告)日：2024-05-16

申请号：US18517318

申请日：2023-11-22

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer KP ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US11954783B2

公开(公告)日：2024-04-09

申请号：US17565114

申请日：2021-12-29

Applicant: Intel Corporation

Inventor： Atsuo Kuwahara ,  Deepak S. Vembar ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Prasoonkumar Surti ,  Murali Ramadoss

IPC: G06T15/00 ,  G06F9/50 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

CPC classification number: G06T15/005 ,  G06F9/5027 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T2215/16

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.