公开(公告)号：US20190044718A1

公开(公告)日：2019-02-07

申请号：US15982278

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew H. Reinders ,  Sudhir K. Satpathy ,  Manoj R. Sastry

IPC: H04L9/30 ,  G06F7/72 ,  G06F7/544

Abstract: In one embodiment, an apparatus includes: a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include: a multiplier circuit comprising a parallel combinatorial multiplier; and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.

公开(公告)号：US20180337780A1

公开(公告)日：2018-11-22

申请号：US15952720

申请日：2018-04-13

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R. Sastry

IPC: H04L9/30 ,  G09C1/00 ,  H04L9/14 ,  G06F7/72

CPC classification number: H04L9/3066 ,  G06F7/725 ,  G09C1/00 ,  H04L9/14 ,  H04L2209/12 ,  H04L2209/24

Abstract: Embodiments of a system for, and method for using, an elliptic curve cryptography integrated circuit are generally described herein. An elliptic curve cryptography (ECC) operation request may be received. One of a plurality of circuit portions may be instructed to perform the ECC operation. The plurality of circuit portions that may be used include a finite field arithmetic circuit portion, an EC point addition and doubler circuit portion, a finite field exponentiation circuit portion, and a point multiplier circuit portion. The result of the ECC operation may then be output.

公开(公告)号：US20180183574A1

公开(公告)日：2018-06-28

申请号：US15392324

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R. Sastry ,  Jesse R. Walker ,  Ravi L. Sahita ,  Abhishek Basak ,  Vedvyas Shanbhogue ,  David M. Durham

IPC: H04L9/06 ,  G06F21/44 ,  G06F21/72

Abstract: Embodiments include a computing processor control flow enforcement system including a processor, a block cipher encryption circuit, and an exclusive-OR (XOR) circuit. The control flow enforcement system uses a block cipher encryption to authenticate a return address when returning from a call or interrupt. The block cipher encryption circuit executes a block cipher encryption on a first number including an identifier to produce a first encrypted result and executes a block cipher encryption on a second number including a return address and a stack location pointer to produce a second encrypted result. The XOR circuit performs an XOR operation on the first encrypted result and the second encrypted result to produce a message authentication code tag.

公开(公告)号：US20250138829A1

公开(公告)日：2025-05-01

申请号：US19009066

申请日：2025-01-03

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry

IPC: G06F9/38 ,  G06F9/30

Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and executing, by execution circuitry, the decoded XOR3PP instruction to determine a first rotational value and a second rotational value, perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value, perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result.

公开(公告)号：US12197921B2

公开(公告)日：2025-01-14

申请号：US18145801

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry

IPC: G06F9/38 ,  G06F9/30

Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3PP instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and executing, by execution circuitry, the decoded XOR3PP instruction to determine a first rotational value and a second rotational value, perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value, perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result.

公开(公告)号：US20250007727A1

公开(公告)日：2025-01-02

申请号：US18344576

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Qian Wang ,  Manoj Sastry

IPC: H04L9/32 ,  H04L9/08

Abstract: Techniques for implementing a hardware engine for stateless hash-based signatures according to a SPHINCS+standard with encryption according to a SHA256 encryption standard are described. In certain examples, a system includes a processor core; and an accelerator coupled to the processor core, the accelerator comprising: one or more hash engine circuits, a coupling to allow for communication between the one or more hash engine circuits and a memory, and hash control circuitry to, for a request to perform a stateless hash-based signature operation on an input, cause performance of a one-time signature scheme function and a forest of random subsets function by the one or more hash engine circuits to generate a resultant.

公开(公告)号：US20250004770A1

公开(公告)日：2025-01-02

申请号：US18346093

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry ,  Rotem Ohana Peretz ,  Regev Shemy

IPC: G06F9/30

Abstract: Circuitry and methods for implementing one or more Keccak permutation instructions are described. In certain examples, a hardware processor (e.g., core) includes decoder circuitry to decode a first instruction into a decoded first instruction, the first instruction comprising identifiers of a first register to store a first word of Keccak state value, a second register to store a second word of Keccak state value and a third word of Keccak state value, and a third register to store a fourth word of Keccak state value and a fifth word of Keccak state value according to a SHA3 standard, and an opcode to indicate vector execution circuitry comprising a plurality of lanes is to use only a single lane of the plurality of lanes to perform a column parities operation of a theta step of a Keccak permutation according to the SHA3 standard to determine a computed parity value for an input of the first word of Keccak state value, the second word of Keccak state value, the third word of Keccak state value, the fourth word of Keccak state value, and the fifth word of Keccak state value, and store the computed parity value into an unused upper word of the first register; and the vector execution circuitry to execute the decoded first instruction according to the opcode.

公开(公告)号：US12120227B2

公开(公告)日：2024-10-15

申请号：US18049522

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Marcio Juliato ,  Manoj Sastry

IPC: H04L9/08 ,  H04L9/06

CPC classification number: H04L9/0861 ,  H04L9/0643 ,  H04L9/0825

Abstract: A method comprises receiving an image of an update for a software module, a rate parameter, an index parameter, and a public key, generating a 32-byte aligned string, computing a state parameter using the 32-byte aligned string, generating a modified message representative, computing a Merkle Tree root node, and in response to a determination that the Merkle Tree root node matches the public key, forwarding, to a remote device, the image of the update for a software module, the state parameter; and the modified message representative.

公开(公告)号：US12086596B2

公开(公告)日：2024-09-10

申请号：US18164738

申请日：2023-02-06

Applicant: Intel Corporation

Inventor： Christoph Dobraunig ,  Santosh Ghosh ,  Manoj Sastry

IPC: G06F9/30

CPC classification number: G06F9/30196 ,  G06F9/30029 ,  G06F9/30032

Abstract: Techniques are described for an instruction for a conditional rotate and XOR operation in a single instruction and triple input bitwise logical operations in a single instruction in an instruction set of a computing system.

公开(公告)号：US12058261B2

公开(公告)日：2024-08-06

申请号：US17480360

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Dumitru-Daniel Dinu ,  Avinash L. Varna ,  Manoj Sastry

IPC: H04L9/30 ,  G06F17/14 ,  H04L9/08 ,  H04L9/32

CPC classification number: H04L9/3093 ,  H04L9/0869 ,  H04L9/3026 ,  H04L9/3247

Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform a number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format. The plurality of compute nodes comprises at least a first butterfly circuit to perform a series of butterfly calculations on input data and a randomizing circuitry to randomize an order of the series of butterfly calculations.