公开(公告)号：WO1997023045A1

公开(公告)日：1997-06-26

申请号：PCT/US1996020677

申请日：1996-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  WRIGHT, Jeffrey, P. ,  CLOUD, Eugene, H.

IPC: H03K19/017

CPC classification number: H03K19/01721

Abstract: An asynchronous self-adjusting circuit (20) includes an input circuit (22) receiving an input signal and providing an output signal. The input circuit (22) starts to switch the output signal to a first logic level based on the level of the input signal reaching a falling edge adjustable trip point, and starts to switch the output signal to a second logic level base on the level of the input signal reaching a rising edge adjustable trip point. A control circuit (24) dynamically and asynchronously adjusts the falling and rising edge adjustable trip points as a function of a previous value of the input signal to permit the asynchronous self-adjusting circuit to respond quickly to changes in the input signal without causing oscillation of the output signal by asynchronously controlling when the output signal is permitted to again switch logic states one the output signal switches logic states.

Abstract translation: 异步自调整电路（20）包括接收输入信号并提供输出信号的输入电路（22）。 基于输入信号的电平达到下降沿可调跳变点，输入电路（22）开始将输出信号切换到第一逻辑电平，并且基于电平的等级开始将输出信号切换到第二逻辑电平 输入信号达到上升沿可调跳闸点。 控制电路（24）根据输入信号的先前值动态地和异步地调整下降沿和上升沿可调跳变点，以允许异步自调节电路快速响应输入信号的变化而不引起振荡 输出信号通过异步地控制何时允许输出信号再次切换逻辑状态，一个输出信号切换逻辑状态。

公开(公告)号：WO1997022996A1

公开(公告)日：1997-06-26

申请号：PCT/US1996020356

申请日：1996-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  BALL, Michael, B.

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A device (10) and method for increasing integrated circuit density comprising a pair of superimposed dies (12, 14) with a plurality of leads (16) extending between the dies. The device (10) is produced by providing a lower die (12) which has a plurality of bond pads (18) on a face side (22) of the lower die (12). A layer of dielectric or insulative shielding (20) is applied over the lower die face side (22). Leads (16) are applied to an upper surface of the shielding layer (20). A plurality of lower die bond wires (26) are attached between the lower die bond pads (18) and an upper surface (28) of their respective leads. A second layer of dielectric or insulative shielding (30) is applied over the leads (16) and the portion of the lower die bond wires (26) extending over the lead upper surfaces (28). A back side (32) of the upper die (14) is adhered to an upper surface (34) of the second shielding layer (30). A plurality of upper die bond wires (36) are attached between a plurality of bond pads (38) on a face side of the upper die (14) and the upper surface of their respective leads (16).

Abstract translation: 一种用于提高集成电路密度的装置（10）和方法，包括一对具有在所述管芯之间延伸的多个引线（16）的叠加管芯（12,14）。 通过在下模（12）的表面（22）上提供具有多个接合焊盘（18）的下模（12）来制造装置（10）。 一层电介质或绝缘屏蔽（20）施加在下模面（22）上。 引线（16）被施加到屏蔽层（20）的上表面。 多个下模接合线（26）安装在下模接合焊盘（18）和它们各自引线的上表面（28）之间。 在引线（16）上施加第二层电介质或绝缘屏蔽层（30），并且在引线上表面（28）上延伸的下模接合线（26）的部分。 上模（14）的背面（32）粘附到第二屏蔽层（30）的上表面（34）上。 多个上模接合线（36）安装在上模（14）的表面侧上的多个接合焊盘（38）和它们各自的引线（16）的上表面之间。

公开(公告)号：WO1997020348A1

公开(公告)日：1997-06-05

申请号：PCT/US1996018886

申请日：1996-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  CASPER, Stephen, L. ,  MA, Manny, K., F. ,  SHER, Joseph, C.

IPC: H01L27/02

CPC classification number: H01L27/0288

Abstract: An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.

Abstract translation: 用于I / O焊盘的ESD保护结构由在晶体管的有源区域下面的阱电阻器形成。 阱电阻器与有源区域串联耦合，并提供额外的电阻，这有助于保护晶体管免受ESD事件的影响。 有源区域上的金属导体具有通过绝缘层形成的有源区域的多个触点，以接触有源区域。 与晶体管的有源区相邻的附加有源区也耦合到阱电阻器以及向I / O焊盘提供导体的导电层。 有源区域被硅化以降低其电阻并增加晶体管的开关速度。 n阱电阻器串联耦合以提供相对于有源区域的大电阻以减少ESD事件的影响。

公开(公告)号：WO1997018587A1

公开(公告)日：1997-05-22

申请号：PCT/US1996018049

申请日：1996-11-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SHER, Joseph, C. ,  MA, Manny, K., F., ,  CASPER, Stephen, L.

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and apparatus for increasing the number of contacts provided between two conductive layers separated by an insulator in a semiconductor integrated circuit chip is disclosed. In a first row of contacts, each contact (314) in the row is separated by a distance, L. A second row of contacts is formed parallel to the first row. Each contact (310, 312) in the second row is spaced a distance of L from other contacts in the row. However, the second row is staggered from the first row, such that each contact is halfway between adjacent contacts in the first row. Each contact in the second row is located a distance of L from the two closest contacts in the first row. Successive rows are formed in similar staggered manner.

Abstract translation: 公开了一种用于增加在半导体集成电路芯片中由绝缘体隔开的两个导电层之间提供的触点数量的方法和装置。 在第一排触点中，该行中的每个触点（314）被隔开距离L.L。第二行触点形成为平行于第一行。 第二排中的每个触点（310,312）与该行中的其它触点隔开一定距离L。 然而，第二行与第一行交错，使得每个触点位于第一行中的相邻触点之间的中间。 第二排中的每个触点位于与第一行中两个最接近的触点的距离L。 连续的行以类似的交错方式形成。

公开(公告)号：WO1997018564A1

公开(公告)日：1997-05-22

申请号：PCT/US1996018223

申请日：1996-11-13

Applicant: MICRON TECHNOLOGY, INC. ,  SEYYEDY, Mirmajid

Inventor： MICRON TECHNOLOGY, INC. ,  SEYYEDY, Mirmajid

IPC: G11C11/409

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12

Abstract: A low voltage high density memory device is described. The memory device uses isolation transistors to adjust the voltage stored on memory cells. The memory device is designed to reduce the differential voltage between memory cells storing different data states. A method is described for reducing leakage current of the memory cells to decrease the need for excessive refresh operations. The memory device is described as operating on a one volt supply and producing a 250 mv digit line swing.

Abstract translation: 描述了低电压高密度存储器件。 存储器件使用隔离晶体管来调节存储单元中存储的电压。 存储器件旨在减少存储不同数据状态的存储单元之间的差分电压。 描述了一种用于减少存储器单元的泄漏电流以减少对过度刷新操作的需要的方法。 存储器件被描述为在一伏特电源上工作并产生250mv数字线的摆幅。

公开(公告)号：WO1997008703A1

公开(公告)日：1997-03-06

申请号：PCT/US1996014002

申请日：1996-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  HUSH, Glen, E. ,  THOMANN, Mark, D.

IPC: G11C07/00

CPC classification number: H04L12/5601 ,  G11C7/1075 ,  H04L49/108 ,  H04L2012/5681 ,  H04Q11/0478

Abstract: A multiport memory is described which includes a random access memory (RAM) and serial access memories (SAMs). The multiport memory is well suited for storing asynchronous transfer mode (ATM) data cells. Control circuitry is provided to allow the multiport memory to be easily configured for operating at different input data rates. This is accomplished by configuring several of the SAMs to store a portion of an input ATM cell on an input clock cycle. The full ATM cell is stored in less clock cycles and can be transferred from the SAMs to the RAM in a single transfer cycle.

Abstract translation: 描述了包括随机存取存储器（RAM）和串行存取存储器（SAM））的多端口存储器。 多端口存储器非常适用于存储异步传输模式（ATM）数据单元。 提供控制电路以允许容易地配置多端口存储器，以便以不同的输入数据速率进行操作。 这通过配置几个SAM来在输入时钟周期上存储输入ATM信元的一部分来实现。 完整的ATM信元以更少的时钟周期存储，并且可以在单个传输周期内从SAM传输到RAM。

公开(公告)号：WO1997006560A1

公开(公告)日：1997-02-20

申请号：PCT/US1996012695

申请日：1996-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MANNING, H., Monte

IPC: H01L23/48

CPC classification number: H01L21/76895 ,  H01L21/76889 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for fabrication of a local interconnect polycide layer for connection of active devices within a silicon substrate. A polysilicon layer (20) is deposited over the insulating layer (15) before contact openings (25) are etched. Metal silicide (40) such as tungsten silicide is then deposited over the insulating layer and into the contact opening, forming direct contact between the silicide layer and the active areas. The polysilicon layer acts merely as an adhesion layer while the silicide serves as an interconnect. Ohmic contact is achieved without the need to dope the polysilicon or the silicide.

Abstract translation: 提供了一种用于制造用于连接硅衬底内的有源器件的局部互连多晶硅化物层的方法。 在蚀刻接触开口（25）之前，在绝缘层（15）上沉积多晶硅层（20）。 然后将金属硅化物（40）如硅化钨沉积在绝缘层上并进入接触开口，形成硅化物层与有源区之间的直接接触。 多晶硅层仅用作粘合层，而硅化物用作互连。 实现了欧姆接触，而不需要掺杂多晶硅或硅化物。

公开(公告)号：WO1996041485A2

公开(公告)日：1996-12-19

申请号：PCT/US1995015861

申请日：1995-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  THOMANN, Mark, R. ,  VO, Huy, Thanh

IPC: H04Q00/00

CPC classification number: G06F9/3824 ,  H04L2012/5616 ,  H04L2012/5647 ,  H04Q11/0478

Abstract: A multiport interface for digital communication systems having pipelined multiplexing of port instructions for increased throughput. The multiport interface includes an analog delay for independent timing of asynchronous operations, such as memory accesses. The multiport interface also has an instruction pipeline and multiplexer to coordinate a number of port instructions.

Abstract translation: 一种用于数字通信系统的多端口接口，具有用于提高吞吐量的端口指令的流水线复用。 多端口接口包括用于异步操作的独立定时的模拟延迟，诸如存储器访问。 多端口接口还具有指令流水线和多路复用器来协调多个端口指令。

公开(公告)号：WO1996041424A1

公开(公告)日：1996-12-19

申请号：PCT/US1995016179

申请日：1995-12-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  THOMANN, Mark, R. ,  VO, Huy, Thanh ,  INGALLS, Charles, L.

IPC: H03M13/00

CPC classification number: H04L1/0057 ,  G06F11/10 ,  G06F13/38 ,  H03M13/091 ,  H03M13/37

Abstract: A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle. The system includes an input buffer, a latch, a CRC generator and write circuit, a status register, and an edit buffer which are connected on a common bus structure to provide maximum flexibility in performing error correction. The data flow may be programmed to bypass the CRC module if the data does not require error correction. Additionally, the raw data may be processed to accommodata different data protocols, so that the system is not restricted to a single data protocol.

Abstract translation: 用于数字系统的高速循环冗余校验系统。 高速循环冗余校验系统为不同的数据协议提供可编程的纠错功能。 高速循环冗余校验系统提供可编程数据路径，用于最小化开销和最大化吞吐量。 该系统在单个循环中支持多个操作。 该系统包括连接在公共总线结构上的输入缓冲器，锁存器，CRC发生器和写入电路，状态寄存器和编辑缓冲器，以在执行纠错时提供最大的灵活性。 如果数据不需要纠错，则数据流可以被编程为绕过CRC模块。 此外，原始数据可以被处理以适应不同的数据协议，使得系统不限于单个数据协议。

公开(公告)号：WO1996041381A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009069

申请日：1996-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  GONZALES, Fernando ,  TURI, Ray

IPC: H01L29/861

CPC classification number: H01L27/24

Abstract: The invention provides a vertically oriented diode for use in delivering large amounts of current to a variable resistance element in a multi-state memory cell. The vertical diode is disposed in a diode container (20) extending downwardly from the top of a tall oxide stack into a deep trench in single crystal silicon. The diode is formed of a combination of single crystal and/or polycrystalline silicon layers (22, 24) disposed vertically inside the diode container. The memory element is formed above the diode to complete a memory cell. The vertical construction of the diode provides a large diode surface area capable of generating a very large current flow through the memory element, as is required for programming. In this way, a highly effective diode can be created for delivering a large current without requiring the substrate surface space normally associated with such large diodes.

Abstract translation: 本发明提供了一种垂直取向的二极管，用于将大量电流传送到多状态存储单元中的可变电阻元件。 垂直二极管设置在从高氧化物堆叠的顶部向下延伸到单晶硅中的深沟槽的二极管容器（20）中。 二极管由垂直设置在二极管容器内的单晶和/或多晶硅层（22,24）的组合形成。 存储元件形成在二极管上方以完成存储单元。 二极管的垂直结构提供了大的二极管表面积，能够产生通过存储元件的非常大的电流，如编程所需要的那样。 以这种方式，可以产生高效的二极管来传递大电流，而不需要通常与这种大二极管相关联的衬底表面空间。