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公开(公告)号：AU624745B2
公开(公告)日：1992-06-18
申请号：AU6524790
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：BR9104906A
公开(公告)日：1992-04-14
申请号：BR9104906
申请日：1991-02-25
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A , WHITE RICHARD E
Abstract: An encryption circuit that operates with substantially zero delay. Using programmable keys and polynomials, the encryption algorithm can be constantly changed to thwart any unintended receiving parties from decoding the data. A key (101) and a polynomial (102) are loaded into registers. The key is then loaded into a shift register and shifted through XOR gates (106) at a programmable rate. The other input of the XOR gates come from the result of ANDing (103) a disable signal, the polynomial register (102), and the last stage of the shift register (104). Eight bits of the shift register outputs are XOR'ed with the input data to be encrypted. The output of these XOR gates (105) is the encrypted data.
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公开(公告)号：CS58191A3
公开(公告)日：1992-02-19
申请号：CS58191
申请日：1991-03-06
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A , WHITE RICHARD E
Abstract: An encryption circuit that operates with substantially zero delay. Using programmable keys and polynomials, the encryption algorithm can be constantly changed to thwart any unintended receiving parties from decoding the data. A key (101) and a polynomial (102) are loaded into registers. The key is then loaded into a shift register and shifted through XOR gates (106) at a programmable rate. The other input of the XOR gates come from the result of ANDing (103) a disable signal, the polynomial register (102), and the last stage of the shift register (104). Eight bits of the shift register outputs are XOR'ed with the input data to be encrypted. The output of these XOR gates (105) is the encrypted data.
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公开(公告)号：HUT58173A
公开(公告)日：1992-01-28
申请号：HU625890
申请日：1990-09-28
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：BR9006928A
公开(公告)日：1991-10-08
申请号：BR9006928
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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Patent Agency Ranking56.发明专利
公开(公告)号：PL288017A1
公开(公告)日：1991-08-26
申请号：PL28801790
申请日：1990-11-29
Applicant: MOTOROLA INC
Inventor： BERKEN JAMES J , FREEBURG THOMAS A , OGASAWARA ROY T , WHITE RICHARD E , MITZLAFF JAMES E , BEDLEK GREGORY J
Abstract: A wireless in-building telecommunications system for voice and data communications is disclosed having at least one node (101) arranged for linking to the PSTN (151) and at least one digital information source (153, 155, 157, 159) multiplicity of user modules (103) (UM's) linked to the node via a shared RF communications path (107). Each UM is coupled to a voice telephone instrument (127) and to one or more data terminals (165). The UM's communicate with the node by exchanging fast packets via the common RF path (107). The node also includes a fast-packet-switched mechanism controlled by a bandwidth allocating scheme to prevent collisions of packets as they are transmitted between the various units (101, 103) (nodes and/or user modules) that may be accessing the RF path (107). Also disclosed is a method for allocating the required bandwidth to each of the users of the common communications path in a wireless in-building telephone system. The invention provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. It also synchronizes the transfer of the data and the allocation of bus bandwidth.
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公开(公告)号：CS526990A2
公开(公告)日：1991-08-13
申请号：CS526990
申请日：1990-10-26
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A , WHITE RICHARD E , OGASAWARA ROY T , BEDLEK GEORGY J
IPC: H04L20060101 , H04L5/00
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公开(公告)号：HU907687D0
公开(公告)日：1991-06-28
申请号：HU768790
申请日：1990-11-29
Applicant: MOTOROLA INC
Inventor： BERKEN JAMES J , FREEBURG THOMAS A , OGASAWARA ROY T , WHITE RICHARD E , MITZLAFF JAMES E , BEDLEK GREGORY J
Abstract: A wireless in-building telecommunications system for voice and data communications is disclosed having at least one node (101) arranged for linking to the PSTN (151) and at least one digital information source (153, 155, 157, 159) multiplicity of user modules (103) (UM's) linked to the node via a shared RF communications path (107). Each UM is coupled to a voice telephone instrument (127) and to one or more data terminals (165). The UM's communicate with the node by exchanging fast packets via the common RF path (107). The node also includes a fast-packet-switched mechanism controlled by a bandwidth allocating scheme to prevent collisions of packets as they are transmitted between the various units (101, 103) (nodes and/or user modules) that may be accessing the RF path (107). Also disclosed is a method for allocating the required bandwidth to each of the users of the common communications path in a wireless in-building telephone system. The invention provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. It also synchronizes the transfer of the data and the allocation of bus bandwidth.
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公开(公告)号：AU6524790A
公开(公告)日：1991-04-28
申请号：AU6524790
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：EP0667074A4
公开(公告)日：2005-02-09
申请号：EP94923305
申请日：1994-06-27
Applicant: MOTOROLA INC
Inventor： BUCHHOLZ DALE R , DOSS WILLIAM K , HAMILTON R LEE JR , WHITE RICHARD E , ROBBINS KAREN
CPC classification number: H04L47/34 , H04L1/1614 , H04L1/1809 , H04L1/1854 , H04L29/06 , H04L69/324
Abstract: A packet switching system (100) having a packet switch (140) employs an acknowledgment scheme in order assure the delivery of all fragments (310) comprising a fragmented data packet (300) to improve overall system throughput during the handling of packets (310) that require reassembly. When packet fragments (310) are lost, corrupted or otherwise unintelligible to a receiving device (92, 94), the acknowledgment scheme permits retransmission of the missing data. In addition, a second acknowledgment signal is scheduled by system processing resources (110) in order to verify the successful delivery of all retransmitted data.
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