Abstract:
The apparatus includes a cover (10) having a first surface (12) and a second surface opposed to the first surface (12). The second surface has an edge (16) defining a perimeter and a recessed region (18). A wall (20) is in communication with the recess region (18), the wall (20) and at least a portion of the edge (16) define a compartment (22). An electromagnetic interference-attenuating material is disposed in the compartment (22), and a fluid distributing manifold is disposed in the cover (10).
Abstract:
A method of updating a software code in a cable communication system (10) involves the steps of receiving a notification (100) by a cable access unit (30). Next, the cable access unit (30) receives (110) the software code. After receiving (110) the software code the CAU (30) resets (114) and reboots using the software code.
Abstract:
A data link control method including receiving a message (30) for transmission over a cable communications system. The method determines a number of octets in the message (30). When the number of octets is less than or equal to a predetermined number of octets, the method sets a frame length (44) equal to the number of octets and transmits a frame (180) containing the message (30). When the number of octets is greater than the predetermined number, the messages (30) is segmented (32-42), each segment being identified in order with respect to the other segments. The method thereby provides for graceful communications resumption when the transmission of a message is interrupted before completion.
Abstract:
In a Time Division Multiple Access System, multiple offset values are provided to a divider control circuit (213) of a fractional-N synthesizer (200) by utilizing a microprocessor (305). The microprocessor (305) utilizes timeslot information provided to it by a timeslot selector (301), frequency information provided to it by a frequency selector (303) and a read-only memory (307), to provide offset values to the divider control circuit (213).
Abstract:
A control unit (102) efficiently decodes burst signal transmissions in a TDMA-based telecommunication system (100) by decimating down the number of samples requiring processing during symbol detection. The control unit (102) includes a sampling receiver (304) that inputs burst signals from cable access units, converts them to a pair of baseband quadrature signals, I and Q. The sampling receiver (304) also includes an A/D converter (314) that samples the I and Q signals at preferably four times the symbol rate. A digital signal processor circuit (306) produces a timing error signal for substantially all of the samples. The digital processor circuit (306) also accumulates a timing error sum for each of the four samples. The processor circuit (306) selects the optimum sample as the sample between the samples having the largest positive and negative error sums. The processor circuit (306) also includes a pi /4-DQPSK differential detector that processes the optimum sample of each symbol for symbol detection.
Abstract:
A method for transmitting a communication signal (20) having a data rate over a plurality of spread spectrum traffic channels includes determining a first number of traffic channels required to transmit the communication signal at the data rate, and determining a second number of traffic channels (502) available for transmitting the communication signal (20). In response to a comparison of the first number of traffic to the second number of traffic channels, a first traffic channel (54) for transmitting a first portion of the communication signal (50, 51) and a second traffic channel (56) for transmitting a second portion of the communication signal (52, 53) are selected from the second number of traffic channels (502). The selection of the first traffic channel (54) is non deterministic of the selection of the second traffic channel (56).
Abstract:
A decoder (215) implemented in a receiver of a wireless communication system employs an improved method and apparatus for decoding an encoded signal. The receiver sums the energy values (156A, 156B, ...156N) from a plurality of fingers within to produce an aggregate energy value (166). From the aggregate energy value (166), a set of log-likelihood values (207) are generated with a non-linear function generator (205) before being deinterleaved by a deinterleaver (210). The deinterleaved values (213) are input to the decoder (215) which estimates the original signal (178) by incorporating path histories of bits in the estimation of subsequent, related bits. Use of the path histories of bits improves the estimates of the original signal (178), which translates into an increase in the sensitivity of the receiver.
Abstract:
An electrode material for use in a lithium intercalation electrochemical cell. The electrode material is an Li2NiO2 material which may be used either alone, or in combination with conventional lithiated transition metal oxide materials. The electrode material provides a reservoir or excess pool of lithium ions adapted to overcome the irreversible capacity loss typically experienced in current lithium ion batteries.
Abstract:
A computing element (200) in a computational array includes a memory bypass system which performs in a single clock cycle a calculation that requires the result of a previous calculation performed in a previous clock cycle. The computing element has a computational unit (210) which performs calculations and a result memory (240) which stores the results of the calculations. The memory bypass method and system bypasses the result memory (240) when it determines that the result of a calculation is needed as an input to the next calculation to be performed, and provides the result of the calculation directly to the computational unit (210) to perform the next calculation. Otherwise, when the result is not needed as the input in the next calculation, the memory bypass method and system reads the input for the next calculation from the result memory (240).
Abstract:
A reusable housing (700) receives a memory card (702) containing a machine-readable storage medium (714) to interface with a device (704) having a PC card interface (706) within a PC card slot (710). The memory card (702) has a plurality of connection points (716) for externally accessing the machine-readable storage medium (714). The reusable housing (700) includes a housing member (720) which removably receives and retains the memory card (702). A PC card connector (722) is positioned on the housing member (720) to interface with the PC card interface (706) when the housing member (720) is inserted in the PC card slot (710). The reusable housing (700) further includes an interface (724) which connects the plurality of connection points (716) to the PC card connector (722) to facilitate communication between the machine-readable storage medium (714) and the PC card interface (706).