公开(公告)号：JPH1050932A

公开(公告)日：1998-02-20

申请号：JP20344196

申请日：1996-08-01

Applicant: NEC CORP

Inventor： NARITA KAORU ,  FUJII TAKEO

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

Abstract: PROBLEM TO BE SOLVED: To improve the electrostatic breakdown resistance with no lowering of the latchup resistance. SOLUTION: All terminals on a chip are connected to a common wiring through protective elements. Protective elements consists of parallel elements of clamp elements and diodes. The clamp elements connected to a ground terminal (GND terminal) are thyristor elements with clamp voltage Vcl and clamp elements of the terminals excepting for the ground terminal are using bipolar elements with clamp voltage Vc2. And, relations Vc1

公开(公告)号：JPH09223748A

公开(公告)日：1997-08-26

申请号：JP33391996

申请日：1996-12-13

Applicant: NEC CORP

Inventor： NARITA KAORU ,  HORIGUCHI YOKO ,  FUJII TAKEO

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To enable protecting a semiconductor device from electrostatic breakdown, by connecting a drain of a trigger MOS transistor and a collector of an NPN transistor to a terminal, and connecting a gate and a source of the trigger MOS transistor and an emitter of the NPN transistor to a common discharge line. SOLUTION: An input and output wiring 12 is connected with a drain diffusion layer 16. A gate electrode 17 is formed, a source diffusion layer 18 is formed, and a trigger MOS transistor 4 is constituted. The source diffusion layer 18 and the gate electrode 17 are connected to a ground wiring 20. The input and output wiring 12 is connected to a collector diffusion layer 23. Collector diffusion layers 23' are formed sandwiching the source diffusion layer 18 and connected to the input and output wiring 12. Thereby the source diffusion layer 18 is made an emitter diffusion layer, and an NPN transistor 5 is constituted of base regions 24, 24' and the collector diffusion layers 23, 23' which are formed in parallel.

公开(公告)号：JPH0945862A

公开(公告)日：1997-02-14

申请号：JP19333995

申请日：1995-07-28

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/60 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To protect a semiconductor integrated circuit against electrostatic discharge failure caused by impression of negative electrostatic pulses. SOLUTION: An N-type well 2, a P-type diffusion layer 3 formed in the N-type well 2 and connected to an input/output terminal 10, an N-type diffusion layer 4 formed coming into contact with the N-type well 2, a P-type diffusion layer 6 provided confronting the N-type diffusion layer 4, an N-type diffusion layer 5 connected to a common wiring, a resistor 11 connected between an input/output terminal 10 and the N-type diffusion layer 4, and a resistor 12 connected between the common wiring and the P-type diffusion layer 6 are provided to a P-type semiconductor substrate 1.

公开(公告)号：JPH07147384A

公开(公告)日：1995-06-06

申请号：JP31900993

申请日：1993-11-25

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/485 ,  H01L27/06

Abstract: PURPOSE:To prevent junction breakdown from occurring in a shallow diffusion layer when a static electricity pulse is applied to an external terminal which is connected to the shallow diffusion layer. CONSTITUTION:An n-type diffusion layer 102 is formed on the surface of a p-type semiconductor substrate 101 and an aluminum wiring 106 is in contact with the diffusion layer via a contact hole 107 opened at an interlayer insulation film 105. A contact n-type diffusion layer 104 which has a higher impurity concentration and a deeper junction depth is formed directly below the contact part of the aluminum wiring 106. A low-impurity concentration n well 103 is formed outside the contact n-type diffusion layer 104 so that the diffusion layer 104 can be enclosed.

公开(公告)号：JPH06260606A

公开(公告)日：1994-09-16

申请号：JP4619093

申请日：1993-03-08

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/8238 ,  H01L21/822 ,  H01L27/04 ,  H01L27/092 ,  H01L29/74 ,  H01L29/78 ,  H01L29/784

Abstract: PURPOSE:To provide an input protection element with controllability without requiring a special process on formation by protecting an internal circuit efficiently for an excessive voltage of both positive and negative electrodes in a semiconductor device. CONSTITUTION:When the excessive voltage of a positive pole is applied to an input terminal 111, a thyristor of PNPN structure which is formed by a P-type well 103, an N-type well 102, a P-type silicon substrate 101, and a first N-type diffusion layer 107 is turned on. Also, when the excessive voltage of the negative pole is applied to the input terminal, a thyristor in NPNP structure formed by a second N-type diffusion layer 105, a P-type well 103. an N-type well 102, and a first P-type diffusion layer 106 is turned on, thus preventing a high voltage from being applied to the internal circuit.

公开(公告)号：JPH05121727A

公开(公告)日：1993-05-18

申请号：JP27943791

申请日：1991-10-25

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L23/52 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/43

Abstract: PURPOSE:To provide the contact-structure and manufacturing method thereof in simple manufacturing steps and at low resistance even if a semiconductor element is miniaturized. CONSTITUTION:A wiring structure is downward composed of an aluminum base wiring material film 108, an aluminum silicon alloy 107 and a barrier film 104 while the contact part is filled up with the aluminum-silicon alloy film 107. Firstly, polycrystalline silicon is buried in a contact hole and then an aluminum film is formed and heat-treated at 400 deg.C-500 deg.C to be alloyed for the formation of this aluminum-silicon alloy film 107. Through these procedures, the heat treatment at high temperature can be eliminated to mitigate the effect thereof on an element such as transistor, etc., in comparison with the case of filling up the contact hole with the polycrystalline silicon thereby enabling the buried-in contact using a barrier metal to be formed due to the applicable heat-treatment at lower temperature so that the element even if miniaturized may be manufactured in simple steps at low resistance.

公开(公告)号：JPH0393233A

公开(公告)日：1991-04-18

申请号：JP23078789

申请日：1989-09-05

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/322 ,  H01L21/822

Abstract: PURPOSE:To improve the manufacturing yield by subjecting the device to heat treatment after arsenic ion implantation into a silicon substrate. CONSTITUTION:A sacrifice oxide film 3 deposited over a silicon substrate 1 is removed, and arsenic ions are implanted. The substrate is heat-treated in a nitrogen atmosphere and gettered with a heavy metal at a depth clode to the range of arsenic ions. The substrate 1 is etched to remove arsenic ions and heavy metal contamination together with silicon. After a gate oxide film is deposited, a gate electrode 5 is formed. This way of removing heavy metal contamination by arsenic ions can provide devices of excellent yield and high reliability.

公开(公告)号：JPH02281656A

公开(公告)日：1990-11-19

申请号：JP10242189

申请日：1989-04-21

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE:To facilitate the reduction of a memory cell in size by a method wherein a memory cell, which includes a MOS transistor composed of a source region and a drain region selectively deposited on the surface of a semiconductor substrate, a gate insulating film, and a gate electrode and a groove stacked type capacitor formed self-aligned with the gate electrode of the MOS transistor, is provided. CONSTITUTION:A memory cell is provided with a MOS transistor and a groove stacked type capacitor (composed of a storage electrode 109i2, a capacitor insulating film 110i2 on the electrode 109i2, and a capacitor cell plate 111i2) provided self-aligned with the a gate electrode 105i2 of the MOS transistor, where the MOS transistor is composed of the following: a source region 102i2S and a drain region 102id which are both formed of an N -type polycrystalline film and selectively deposited on the surface of a P-type Si semiconductor 102; a gate insulating film 119i2 formed on the side faces of the source region 102i2S and the drain region 102id and on the semiconductor substrate 101 between the source region 102i2S and the drain region 102id; and a gate electrode 105i2 provided onto the gate insulating film 119i2.

公开(公告)号：JPH0294465A

公开(公告)日：1990-04-05

申请号：JP24602488

申请日：1988-09-29

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/822 ,  H01L27/04

Abstract: PURPOSE:To provide a capacity insulating film having improved leakage properties, dielectric strength and aging dielectric breakdown properties by forming the capacity insulating film such that it is thicker at the upper edges of a trench than in the other regions. CONSTITUTION:An oxide film is deposited in an opening formed by etching a silicon nitride film 2. When the structure is dry etched by using the film 2 as a mask, the oxide film 6 is left uneched at the edges of a trench 7 thus formed. When an oxide film 8 is formed by thermal oxidation, the oxide film 8 becomes thicker at the upper edges of the trench 7 than in the other regions. A silicon nitride film 9 is then deposited on the surface of the film 8 including the trench 7 and then a conductive polycrystalline silicon film 10 is deposited on the film 9 to provide a capacity electrode. If electric field is concentrated at the edges of the trench, the capacity section thus obtained can present leakage properties, dielectric strength and aging dielectric breakdown properties equivalent to those of a planar capacity section and can provide a large capacity.

公开(公告)号：JPH01100962A

公开(公告)日：1989-04-19

申请号：JP25901187

申请日：1987-10-13

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE:To spreading an oxide film of uniform thickness on the side surface of a first polycrystalline silicon to be subjected to insulation oxidation, and increase the dielectric strength against a second polycrystalline silicon, by eliminating a second nitride film on the main surface and the side surface of a first polycrystalline silicon to be subjected to insulating oxidation and a part of a first nitride film, and forming an oxide film on the eliminated part. CONSTITUTION:A capacitance oxide film 12, a first silicon nitride film 13, and a capacitance plate 14 are formed on a semiconductor substrate 11. After a second nitride film 15 is spread, it is coated with a silica film 16, and heat- treated. Then, by nitride film etching, the second silicon nitride film 15 spread on the main surface and the side surface part of the polycrystalline silicon 14, and a part of the silicon nitride film 13 are eliminated. By thermal oxidation method, an insulating oxide film 17 is spread on the main upper surface and the side surface of a capacitance plate 14. Then, by etching, the nitride film 15 and the capacitance oxide film 12 except capacitance part are eliminated. A gate oxide film 18 and a second polycrystalline silicon film 19 are newly spread, and a gate electrode is formed by photoetching method.