公开(公告)号：EP1597667A4

公开(公告)日：2009-01-14

申请号：EP03816195

申请日：2003-08-07

Applicant: QUALCOMM INC

Inventor： RICHARDSON TOM ,  NOVICHKOV VLADIMIR ,  JIN HUI

IPC: H03M13/00 ,  H04L1/00 ,  G06F7/60 ,  G06F7/02 ,  G06F11/00 ,  G06F17/10

CPC classification number: H04L1/005 ,  H03M13/00 ,  H03M13/1102 ,  H03M13/296 ,  H03M13/3707 ,  H03M13/6325 ,  H03M13/658

Abstract: Methods and apparatus for scaling soft values (214) as part of an error correction decoding process are described. Accurate decoding depends on use of the appropriate scale factor. Selection and use of the scale factor to scale soft values is designed to improve and/or optimize decoder performance without the need for prior knowledge of the correct scale factor or the actual channel conditions at the time the signal from which the soft values were obtained was transmitted through a communications channel. The techniques of the present invention assumes that the soft values to be processed were transmitted through a communications channel having a quality that can be accurately described by a channel quality value (200). A scale factor is determined from the distribution of soft value (208) to be scaled (212) and an assumption that the channel through which they were transmitted was of the quality corresponding to a pre-selected channel quality value (210).

公开(公告)号：CA2672074C

公开(公告)日：2013-10-08

申请号：CA2672074

申请日：2005-07-20

Applicant: QUALCOMM INC

Inventor： RICHARDSON TOM ,  JIN HUI ,  NOVICHKOV VLADIMIR

IPC: H03M13/13 ,  H04W88/02

Abstract: A flexible and relatively hardware efficient LDPC decoder (900) is described. The decoder cai be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process (901). Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths (912) are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor (908) that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused (916).

公开(公告)号：AU2010200854B2

公开(公告)日：2012-05-17

申请号：AU2010200854

申请日：2010-03-05

Applicant: QUALCOMM INC

Inventor： RICHARDSON TOM ,  JIN HUI

IPC: H03M13/00

Abstract: A flexible and relatively hardware efficient LDPC encoder is described (300). The encoder cm be implemented with a level of parallelism which is less than the full parallelism of the code structure 5 used to control the encoding process (301). Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword (354). Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used (3 10). The LDPC encoder can switch between encoding codewords of 10 different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding process (3 10). When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused (308). MEMORY MODULE 314 LDPC ENCODER 318 L 39 321 322 301 31; 320 322323 303 IN N BLK 1 'BLK 2' -____-___-___BLK______K_____u__ N ... OUT K X (N x L) 1 BIT MEMORY LOCATIONS (CODEWORD 302 + STORAGE) K X (N x 1) 1 BIT MEMORY LOCATIONS (TEMP STORAGE) 324 memory access signal MEMORY ADDRESS 316 _N LOGIC r_308 Block address 1 32 Memo52 select signal (k) 340 3 306 N30 address control signal 358 N ELEMENT 342 N ELEMENT 344 (a 0.L) CONTROLLABLE VECTOR M N N -- ' ACCUMULATOR x L-. MODULE -i read/ _328 write K signal (op) CODE ce ro signal (r) 326 350 LIFTING CONTROLLABLE BASED 373 STORAGE DEVICE SELECTION 36 block select SELETIONcontrol signal 354 356 310 First selection module second selection control module control signal (r,) signal read/wrife signal 371 (op) nS 374 CONTROL .u loop con P ro0 3481 code lifting factor control signal (SK) Fig. 3

公开(公告)号：AU2010200776B2

公开(公告)日：2011-03-17

申请号：AU2010200776

申请日：2010-03-02

Applicant: QUALCOMM INC

Inventor： RICHARDSON TOM ,  NOVICHKOV VLADIMIR ,  JIN HUI

IPC: H03M13/00

Abstract: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process.; When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

公开(公告)号：AT495581T

公开(公告)日：2011-01-15

申请号：AT02800936

申请日：2002-10-07

Applicant: QUALCOMM INC

Inventor： RICHARDSON TOM ,  NOVICHKOV VLADIMIR

IPC: G06F11/10 ,  H03M13/11 ,  G06F17/50 ,  G06N3/02 ,  H03M13/00 ,  H03M13/03 ,  H03M13/09 ,  H03M13/19 ,  H03M13/39

Abstract: Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module (1302), subtractor module (1304) and delay pipeline (1306). The accumulator module (1302) generates an accumulated message sum (1316). The accumulated message sum (1316) for a node is stored and then delayed input messages from the delay pipeline (1306) are subtracted there from to generate output messages (1321). The delay pipeline (1306) includes a variable delay element making it possible to sequentially perform processing operations corresponding to nodes of different degrees.

公开(公告)号：AU2005269729B2

公开(公告)日：2010-10-07

申请号：AU2005269729

申请日：2005-07-20

Applicant: QUALCOMM INC

Inventor： JIN HUI ,  RICHARDSON TOM

IPC: H03M13/00

Abstract: A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.

公开(公告)号：DE602006015473D1

公开(公告)日：2010-08-26

申请号：DE602006015473

申请日：2006-07-19

Applicant: QUALCOMM INC

Inventor： LAROIA RAJIV ,  JIN HUI ,  LI JUNYI ,  LANE FRANK A ,  RICHARDSON TOM

IPC: H04B7/26

公开(公告)号：AU2003261440C1

公开(公告)日：2010-06-03

申请号：AU2003261440

申请日：2003-08-07

Applicant: QUALCOMM INC

Inventor： NOVICHKOV VLADIMIR ,  RICHARDSON TOM ,  JIN HUI

IPC: H03M13/00 ,  G06F11/00 ,  H04L1/00

Abstract: Methods and apparatus for scaling soft values as part of an error correction decoding process are described. Accurate decoding depends on use of the appropriate scale factor. Selection and use of the scale factor to scale soft values is designed to improve and/or optimize decoder performance without the need for prior knowledge of the correct scale factor or the actual channel conditions at the time the signal from which the soft values were obtained was transmitted through a communications channel. The techniques of the present invention assume that the soft values to be processed were transmitted through a communications channel having a quality that can be accurately described by a channel quality value. A scale factor is determined from the distribution of soft values to be scaled and an assumption that the channel through which they were transmitted was of the quality corresponding to a preselected channel quality value.

公开(公告)号：AU2004319505C1

公开(公告)日：2010-04-08

申请号：AU2004319505

申请日：2004-10-15

Applicant: QUALCOMM INC

Inventor： LAROIA RAJIV ,  LI JUNYI ,  RICHARDSON TOM

IPC: H04W16/00 ,  H04W36/28 ,  H04L5/02 ,  H04L27/26 ,  H04W16/02 ,  H04W16/24 ,  H04W28/18 ,  H04W48/12

Abstract: Methods and apparatus for implementing a multi-carrier communications system are described. Various approaches to a phased system deployment and system configurations resulting from different levels of deployment are described. In addition mobile node and methods of operating mobile nodes in communications systems that may have different levels of deployment in different cells are described.

公开(公告)号：AU2010200856A1

公开(公告)日：2010-04-01

申请号：AU2010200856

申请日：2010-03-05

Applicant: QUALCOMM INC

Inventor： RICHARDSON TOM ,  JIN HUI

IPC: H03M13/00

Abstract: A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.